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[PATCH] SHPC: Fix SHPC Contoller SERR-INT Register bits access
Current SHPCHP driver doesn't take care of RsvdP/RsvdZ[*] bits in controller SERR-INT register. This might cause unpredicable results. This patch fixes this bug. [*] RsvdP and RsvdZ are defined in SHPC spec as follows: RsvdP - Reserved and Preserved. Register bits of this type are reserved for future use as R/W bits. The value read is undefined. Writes are ignored. Software must follow These rules when accessing RsvdP bits: - Software must ignore RsvdP bits when testing values read from these registers. - Software must not depend on RsvdP bit's ability to retain information when written - Software must always write back the value read in the RsvdP bits when writing one of these registers. RsvdZ - Reserved and Zero. Register bits of this type are reserved for future use as R/WC bits. The value read is undefined. Writes are ignored. Software must follow these rules when accessing RsvdZ bits: - Software must ignore RsvdZ bits when testing values read from these registers. - Software must not depends on a RsvdZ bit's ability to retain information when written. - Software must always write 0 to RsvdZ bits when writing one of these register. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Cc: Kristen Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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795eb5c4a7
commit
e713872369
1 changed files with 20 additions and 5 deletions
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@ -90,6 +90,17 @@
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#define MRLSENSOR 0x40000000
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#define ATTN_BUTTON 0x80000000
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/*
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* Controller SERR-INT Register
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*/
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#define GLOBAL_INTR_MASK (1 << 0)
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#define GLOBAL_SERR_MASK (1 << 1)
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#define COMMAND_INTR_MASK (1 << 2)
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#define ARBITER_SERR_MASK (1 << 3)
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#define COMMAND_DETECTED (1 << 16)
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#define ARBITER_DETECTED (1 << 17)
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#define SERR_INTR_RSVDZ_MASK 0xfffc0000
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/*
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* Logical Slot Register definitions
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*/
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@ -1047,7 +1058,8 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
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/* Mask Global Interrupt Mask - see implementation note on p. 139 */
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/* of SHPC spec rev 1.0*/
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temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
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temp_dword |= 0x00000001;
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temp_dword |= GLOBAL_INTR_MASK;
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temp_dword &= ~SERR_INTR_RSVDZ_MASK;
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shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
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intr_loc2 = shpc_readl(ctrl, INTR_LOC);
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@ -1061,7 +1073,7 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
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* Detect bit in Controller SERR-INT register
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*/
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temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
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temp_dword &= 0xfffdffff;
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temp_dword &= ~SERR_INTR_RSVDZ_MASK;
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shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
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ctrl->cmd_busy = 0;
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wake_up_interruptible(&ctrl->queue);
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@ -1105,7 +1117,7 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
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if (!shpchp_poll_mode) {
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/* Unmask Global Interrupt Mask */
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temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
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temp_dword &= 0xfffffffe;
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temp_dword &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
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shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
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}
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@ -1374,7 +1386,9 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
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/* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
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tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
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dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
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tempdword = 0x0003000f;
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tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
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COMMAND_INTR_MASK | ARBITER_SERR_MASK);
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tempdword &= ~SERR_INTR_RSVDZ_MASK;
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shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
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tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
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dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
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@ -1452,7 +1466,8 @@ int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
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if (!shpchp_poll_mode) {
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/* Unmask all general input interrupts and SERR */
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tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
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tempdword = 0x0000000a;
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tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
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SERR_INTR_RSVDZ_MASK);
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shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
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tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
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dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
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