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clk: meson: meson8b: make the CCF use the glitch-free mali mux
[ Upstream commit8daeaea99c
] The "mali_0" or "mali_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "mali_0" and "mali_1" gates. This makes the CCF switch to the "mali_1" tree when "mali_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the mali clock. This fixes a potential hang when changing the GPU frequency at runtime. Fixes:74e1f2521f
("clk: meson: meson8b: add the GPU clock tree") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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1 changed files with 7 additions and 4 deletions
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@ -1764,8 +1764,11 @@ static struct clk_regmap meson8b_hdmi_sys = {
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/*
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* The MALI IP is clocked by two identical clocks (mali_0 and mali_1)
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* muxed by a glitch-free switch on Meson8b and Meson8m2. Meson8 only
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* has mali_0 and no glitch-free mux.
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* muxed by a glitch-free switch on Meson8b and Meson8m2. The CCF can
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* actually manage this glitch-free mux because it does top-to-bottom
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* updates the each clock tree and switches to the "inactive" one when
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* CLK_SET_RATE_GATE is set.
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* Meson8 only has mali_0 and no glitch-free mux.
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*/
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static const struct clk_hw *meson8b_mali_0_1_parent_hws[] = {
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&meson8b_xtal.hw,
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@ -1830,7 +1833,7 @@ static struct clk_regmap meson8b_mali_0 = {
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&meson8b_mali_0_div.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
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},
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};
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@ -1885,7 +1888,7 @@ static struct clk_regmap meson8b_mali_1 = {
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&meson8b_mali_1_div.hw
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT,
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},
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};
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