ASoC: codecs: lpass: fix incorrect mclk rate

For some reason we ended up with incorrect mclk rate which should be
1920000 instead of 96000, So far we were getting lucky as the same clk
is set to 192000 by wsa and va macro. This issue is discovered when there
is no wsa macro active and only rx or tx path is tested.
Fix this by setting correct rate.

Fixes: c39667ddcf ("ASoC: codecs: lpass-tx-macro: add support for lpass tx macro")
Fixes: af3d54b997 ("ASoC: codecs: lpass-rx-macro: add support for lpass rx macro")
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20230209122806.18923-7-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Srinivas Kandagatla 2023-02-09 12:28:04 +00:00 committed by Mark Brown
parent 1dc3459009
commit e762143437
No known key found for this signature in database
GPG key ID: 24D68B725D5487D0
2 changed files with 4 additions and 4 deletions

View file

@ -366,7 +366,7 @@
#define CDC_RX_DSD1_CFG2 (0x0F8C)
#define RX_MAX_OFFSET (0x0F8C)
#define MCLK_FREQ 9600000
#define MCLK_FREQ 19200000
#define RX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
@ -3579,7 +3579,7 @@ static int rx_macro_probe(struct platform_device *pdev)
/* set MCLK and NPL rates */
clk_set_rate(rx->mclk, MCLK_FREQ);
clk_set_rate(rx->npl, 2 * MCLK_FREQ);
clk_set_rate(rx->npl, MCLK_FREQ);
ret = clk_prepare_enable(rx->macro);
if (ret)

View file

@ -203,7 +203,7 @@
#define TX_MACRO_AMIC_UNMUTE_DELAY_MS 100
#define TX_MACRO_DMIC_HPF_DELAY_MS 300
#define TX_MACRO_AMIC_HPF_DELAY_MS 300
#define MCLK_FREQ 9600000
#define MCLK_FREQ 19200000
enum {
TX_MACRO_AIF_INVALID = 0,
@ -2014,7 +2014,7 @@ static int tx_macro_probe(struct platform_device *pdev)
/* set MCLK and NPL rates */
clk_set_rate(tx->mclk, MCLK_FREQ);
clk_set_rate(tx->npl, 2 * MCLK_FREQ);
clk_set_rate(tx->npl, MCLK_FREQ);
ret = clk_prepare_enable(tx->macro);
if (ret)