From e77da13b8e3626fc6d01287fba7c1eee4ebfe018 Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 7 Mar 2023 21:10:54 +0000 Subject: [PATCH] riscv: dts: microchip: fix the mpfs' mailbox regs The mailbox on PolarFire SoC should really have three reg properties, not two. Without splitting into three sections, the system controller's QSPI cannot be accessed as it sits inside the current first range. The driver & binding have been adapted to account for both two & three ranges, so fix the dts too. Acked-by: Palmer Dabbelt Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 23b7b05ee291..104504352e99 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -501,7 +501,8 @@ usb: usb@20201000 { mbox: mailbox@37020000 { compatible = "microchip,mpfs-mailbox"; - reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; + reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, + <0x0 0x37020800 0x0 0x100>; interrupt-parent = <&plic>; interrupts = <96>; #mbox-cells = <1>;