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amd-xgbe: Add ECC status support for the device memory
Some versions of the amd-xgbe device are capable of reporting ECC error information back to the driver. Add support to process, track and report on this information. Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Lendacky, Thomas
David S. Miller
parent
4c70dd8ac9
commit
e78332b228
7 changed files with 340 additions and 3 deletions
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@ -178,6 +178,7 @@ config AMD_XGBE
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select BITREVERSE
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select CRC32
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select PTP_1588_CLOCK
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select AMD_XGBE_HAVE_ECC if X86
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---help---
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This driver supports the AMD 10GbE Ethernet device found on an
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AMD SoC.
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@ -195,4 +196,8 @@ config AMD_XGBE_DCB
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If unsure, say N.
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config AMD_XGBE_HAVE_ECC
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bool
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default n
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endif # NET_VENDOR_AMD
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@ -920,6 +920,10 @@
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#define XP_PROP_5 0x0014
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#define XP_MAC_ADDR_LO 0x0020
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#define XP_MAC_ADDR_HI 0x0024
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#define XP_ECC_ISR 0x0030
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#define XP_ECC_IER 0x0034
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#define XP_ECC_CNT0 0x003c
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#define XP_ECC_CNT1 0x0040
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#define XP_DRIVER_INT_REQ 0x0060
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#define XP_DRIVER_INT_RO 0x0064
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#define XP_DRIVER_SCRATCH_0 0x0068
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@ -935,6 +939,42 @@
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#define XP_DRIVER_SCRATCH_0_COMMAND_WIDTH 8
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#define XP_DRIVER_SCRATCH_0_SUB_COMMAND_INDEX 8
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#define XP_DRIVER_SCRATCH_0_SUB_COMMAND_WIDTH 8
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#define XP_ECC_CNT0_RX_DED_INDEX 24
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#define XP_ECC_CNT0_RX_DED_WIDTH 8
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#define XP_ECC_CNT0_RX_SEC_INDEX 16
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#define XP_ECC_CNT0_RX_SEC_WIDTH 8
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#define XP_ECC_CNT0_TX_DED_INDEX 8
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#define XP_ECC_CNT0_TX_DED_WIDTH 8
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#define XP_ECC_CNT0_TX_SEC_INDEX 0
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#define XP_ECC_CNT0_TX_SEC_WIDTH 8
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#define XP_ECC_CNT1_DESC_DED_INDEX 8
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#define XP_ECC_CNT1_DESC_DED_WIDTH 8
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#define XP_ECC_CNT1_DESC_SEC_INDEX 0
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#define XP_ECC_CNT1_DESC_SEC_WIDTH 8
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#define XP_ECC_IER_DESC_DED_INDEX 0
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#define XP_ECC_IER_DESC_DED_WIDTH 1
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#define XP_ECC_IER_DESC_SEC_INDEX 1
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#define XP_ECC_IER_DESC_SEC_WIDTH 1
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#define XP_ECC_IER_RX_DED_INDEX 2
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#define XP_ECC_IER_RX_DED_WIDTH 1
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#define XP_ECC_IER_RX_SEC_INDEX 3
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#define XP_ECC_IER_RX_SEC_WIDTH 1
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#define XP_ECC_IER_TX_DED_INDEX 4
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#define XP_ECC_IER_TX_DED_WIDTH 1
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#define XP_ECC_IER_TX_SEC_INDEX 5
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#define XP_ECC_IER_TX_SEC_WIDTH 1
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#define XP_ECC_ISR_DESC_DED_INDEX 0
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#define XP_ECC_ISR_DESC_DED_WIDTH 1
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#define XP_ECC_ISR_DESC_SEC_INDEX 1
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#define XP_ECC_ISR_DESC_SEC_WIDTH 1
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#define XP_ECC_ISR_RX_DED_INDEX 2
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#define XP_ECC_ISR_RX_DED_WIDTH 1
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#define XP_ECC_ISR_RX_SEC_INDEX 3
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#define XP_ECC_ISR_RX_SEC_WIDTH 1
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#define XP_ECC_ISR_TX_DED_INDEX 4
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#define XP_ECC_ISR_TX_DED_WIDTH 1
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#define XP_ECC_ISR_TX_SEC_INDEX 5
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#define XP_ECC_ISR_TX_SEC_WIDTH 1
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#define XP_MAC_ADDR_HI_VALID_INDEX 31
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#define XP_MAC_ADDR_HI_VALID_WIDTH 1
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#define XP_PROP_0_CONN_TYPE_INDEX 28
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@ -724,6 +724,65 @@ static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
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XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff);
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}
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static void xgbe_enable_ecc_interrupts(struct xgbe_prv_data *pdata)
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{
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unsigned int ecc_isr, ecc_ier = 0;
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if (!pdata->vdata->ecc_support)
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return;
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/* Clear all the interrupts which are set */
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ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
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XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
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/* Enable ECC interrupts */
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XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 1);
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XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 1);
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XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 1);
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XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 1);
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XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 1);
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XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 1);
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XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
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}
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static void xgbe_disable_ecc_ded(struct xgbe_prv_data *pdata)
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{
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unsigned int ecc_ier;
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ecc_ier = XP_IOREAD(pdata, XP_ECC_IER);
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/* Disable ECC DED interrupts */
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XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_DED, 0);
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XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_DED, 0);
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XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_DED, 0);
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XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
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}
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static void xgbe_disable_ecc_sec(struct xgbe_prv_data *pdata,
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enum xgbe_ecc_sec sec)
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{
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unsigned int ecc_ier;
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ecc_ier = XP_IOREAD(pdata, XP_ECC_IER);
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/* Disable ECC SEC interrupt */
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switch (sec) {
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case XGBE_ECC_SEC_TX:
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XP_SET_BITS(ecc_ier, XP_ECC_IER, TX_SEC, 0);
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break;
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case XGBE_ECC_SEC_RX:
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XP_SET_BITS(ecc_ier, XP_ECC_IER, RX_SEC, 0);
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break;
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case XGBE_ECC_SEC_DESC:
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XP_SET_BITS(ecc_ier, XP_ECC_IER, DESC_SEC, 0);
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break;
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}
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XP_IOWRITE(pdata, XP_ECC_IER, ecc_ier);
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}
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static int xgbe_set_speed(struct xgbe_prv_data *pdata, int speed)
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{
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unsigned int ss;
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@ -3294,6 +3353,11 @@ static int xgbe_init(struct xgbe_prv_data *pdata)
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xgbe_config_mmc(pdata);
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xgbe_enable_mac_interrupts(pdata);
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/*
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* Initialize ECC related features
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*/
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xgbe_enable_ecc_interrupts(pdata);
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DBGPR("<--xgbe_init\n");
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return 0;
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@ -3399,5 +3463,9 @@ void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
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hw_if->set_rss_hash_key = xgbe_set_rss_hash_key;
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hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table;
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/* For ECC */
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hw_if->disable_ecc_ded = xgbe_disable_ecc_ded;
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hw_if->disable_ecc_sec = xgbe_disable_ecc_sec;
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DBGPR("<--xgbe_init_function_ptrs\n");
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}
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@ -114,6 +114,7 @@
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <linux/tcp.h>
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#include <linux/if_vlan.h>
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@ -126,8 +127,35 @@
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#include "xgbe.h"
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#include "xgbe-common.h"
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static unsigned int ecc_sec_info_threshold = 10;
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static unsigned int ecc_sec_warn_threshold = 10000;
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static unsigned int ecc_sec_period = 600;
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static unsigned int ecc_ded_threshold = 2;
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static unsigned int ecc_ded_period = 600;
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#ifdef CONFIG_AMD_XGBE_HAVE_ECC
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/* Only expose the ECC parameters if supported */
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module_param(ecc_sec_info_threshold, uint, S_IWUSR | S_IRUGO);
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MODULE_PARM_DESC(ecc_sec_info_threshold,
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" ECC corrected error informational threshold setting");
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module_param(ecc_sec_warn_threshold, uint, S_IWUSR | S_IRUGO);
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MODULE_PARM_DESC(ecc_sec_warn_threshold,
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" ECC corrected error warning threshold setting");
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module_param(ecc_sec_period, uint, S_IWUSR | S_IRUGO);
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MODULE_PARM_DESC(ecc_sec_period, " ECC corrected error period (in seconds)");
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module_param(ecc_ded_threshold, uint, S_IWUSR | S_IRUGO);
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MODULE_PARM_DESC(ecc_ded_threshold, " ECC detected error threshold setting");
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module_param(ecc_ded_period, uint, S_IWUSR | S_IRUGO);
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MODULE_PARM_DESC(ecc_ded_period, " ECC detected error period (in seconds)");
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#endif
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static int xgbe_one_poll(struct napi_struct *, int);
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static int xgbe_all_poll(struct napi_struct *, int);
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static void xgbe_stop(struct xgbe_prv_data *);
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static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
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{
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@ -308,6 +336,107 @@ static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
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xgbe_disable_rx_tx_int(pdata, channel);
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}
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static bool xgbe_ecc_sec(struct xgbe_prv_data *pdata, unsigned long *period,
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unsigned int *count, const char *area)
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{
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if (time_before(jiffies, *period)) {
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(*count)++;
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} else {
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*period = jiffies + (ecc_sec_period * HZ);
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*count = 1;
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}
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if (*count > ecc_sec_info_threshold)
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dev_warn_once(pdata->dev,
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"%s ECC corrected errors exceed informational threshold\n",
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area);
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if (*count > ecc_sec_warn_threshold) {
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dev_warn_once(pdata->dev,
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"%s ECC corrected errors exceed warning threshold\n",
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area);
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return true;
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}
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return false;
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}
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static bool xgbe_ecc_ded(struct xgbe_prv_data *pdata, unsigned long *period,
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unsigned int *count, const char *area)
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{
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if (time_before(jiffies, *period)) {
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(*count)++;
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} else {
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*period = jiffies + (ecc_ded_period * HZ);
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*count = 1;
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}
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if (*count > ecc_ded_threshold) {
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netdev_alert(pdata->netdev,
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"%s ECC detected errors exceed threshold\n",
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area);
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return true;
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}
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return false;
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}
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static irqreturn_t xgbe_ecc_isr(int irq, void *data)
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{
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struct xgbe_prv_data *pdata = data;
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unsigned int ecc_isr;
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bool stop = false;
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/* Mask status with only the interrupts we care about */
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ecc_isr = XP_IOREAD(pdata, XP_ECC_ISR);
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ecc_isr &= XP_IOREAD(pdata, XP_ECC_IER);
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netif_dbg(pdata, intr, pdata->netdev, "ECC_ISR=%#010x\n", ecc_isr);
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if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_DED)) {
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stop |= xgbe_ecc_ded(pdata, &pdata->tx_ded_period,
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&pdata->tx_ded_count, "TX fifo");
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}
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if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_DED)) {
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stop |= xgbe_ecc_ded(pdata, &pdata->rx_ded_period,
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&pdata->rx_ded_count, "RX fifo");
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}
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if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_DED)) {
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stop |= xgbe_ecc_ded(pdata, &pdata->desc_ded_period,
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&pdata->desc_ded_count,
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"descriptor cache");
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}
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if (stop) {
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pdata->hw_if.disable_ecc_ded(pdata);
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schedule_work(&pdata->stopdev_work);
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goto out;
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}
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if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, TX_SEC)) {
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if (xgbe_ecc_sec(pdata, &pdata->tx_sec_period,
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&pdata->tx_sec_count, "TX fifo"))
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pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_TX);
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}
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if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, RX_SEC))
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if (xgbe_ecc_sec(pdata, &pdata->rx_sec_period,
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&pdata->rx_sec_count, "RX fifo"))
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pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_RX);
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if (XP_GET_BITS(ecc_isr, XP_ECC_ISR, DESC_SEC))
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if (xgbe_ecc_sec(pdata, &pdata->desc_sec_period,
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&pdata->desc_sec_count, "descriptor cache"))
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pdata->hw_if.disable_ecc_sec(pdata, XGBE_ECC_SEC_DESC);
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out:
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/* Clear all ECC interrupts */
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XP_IOWRITE(pdata, XP_ECC_ISR, ecc_isr);
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return IRQ_HANDLED;
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}
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static irqreturn_t xgbe_isr(int irq, void *data)
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{
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struct xgbe_prv_data *pdata = data;
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@ -397,6 +526,10 @@ static irqreturn_t xgbe_isr(int irq, void *data)
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if (pdata->dev_irq == pdata->an_irq)
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pdata->phy_if.an_isr(irq, pdata);
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/* If there is not a separate ECC irq, handle it here */
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if (pdata->vdata->ecc_support && (pdata->dev_irq == pdata->ecc_irq))
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xgbe_ecc_isr(irq, pdata);
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isr_done:
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return IRQ_HANDLED;
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}
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@ -679,6 +812,16 @@ static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
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return ret;
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}
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if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq)) {
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ret = devm_request_irq(pdata->dev, pdata->ecc_irq, xgbe_ecc_isr,
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0, pdata->ecc_name, pdata);
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if (ret) {
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netdev_alert(netdev, "error requesting ecc irq %d\n",
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pdata->ecc_irq);
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goto err_dev_irq;
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}
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}
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if (!pdata->per_channel_irq)
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return 0;
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@ -695,17 +838,21 @@ static int xgbe_request_irqs(struct xgbe_prv_data *pdata)
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if (ret) {
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netdev_alert(netdev, "error requesting irq %d\n",
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channel->dma_irq);
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goto err_irq;
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goto err_dma_irq;
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}
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}
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return 0;
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err_irq:
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err_dma_irq:
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/* Using an unsigned int, 'i' will go to UINT_MAX and exit */
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for (i--, channel--; i < pdata->channel_count; i--, channel--)
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devm_free_irq(pdata->dev, channel->dma_irq, channel);
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if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
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devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
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err_dev_irq:
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devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
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return ret;
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@ -718,6 +865,9 @@ static void xgbe_free_irqs(struct xgbe_prv_data *pdata)
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devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
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if (pdata->vdata->ecc_support && (pdata->dev_irq != pdata->ecc_irq))
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devm_free_irq(pdata->dev, pdata->ecc_irq, pdata);
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if (!pdata->per_channel_irq)
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return;
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@ -919,6 +1069,8 @@ static int xgbe_start(struct xgbe_prv_data *pdata)
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xgbe_start_timers(pdata);
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queue_work(pdata->dev_workqueue, &pdata->service_work);
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clear_bit(XGBE_STOPPED, &pdata->dev_state);
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DBGPR("<--xgbe_start\n");
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return 0;
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@ -945,6 +1097,9 @@ static void xgbe_stop(struct xgbe_prv_data *pdata)
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DBGPR("-->xgbe_stop\n");
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if (test_bit(XGBE_STOPPED, &pdata->dev_state))
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return;
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netif_tx_stop_all_queues(netdev);
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xgbe_stop_timers(pdata);
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@ -970,9 +1125,29 @@ static void xgbe_stop(struct xgbe_prv_data *pdata)
|
|||
netdev_tx_reset_queue(txq);
|
||||
}
|
||||
|
||||
set_bit(XGBE_STOPPED, &pdata->dev_state);
|
||||
|
||||
DBGPR("<--xgbe_stop\n");
|
||||
}
|
||||
|
||||
static void xgbe_stopdev(struct work_struct *work)
|
||||
{
|
||||
struct xgbe_prv_data *pdata = container_of(work,
|
||||
struct xgbe_prv_data,
|
||||
stopdev_work);
|
||||
|
||||
rtnl_lock();
|
||||
|
||||
xgbe_stop(pdata);
|
||||
|
||||
xgbe_free_tx_data(pdata);
|
||||
xgbe_free_rx_data(pdata);
|
||||
|
||||
rtnl_unlock();
|
||||
|
||||
netdev_alert(pdata->netdev, "device stopped\n");
|
||||
}
|
||||
|
||||
static void xgbe_restart_dev(struct xgbe_prv_data *pdata)
|
||||
{
|
||||
DBGPR("-->xgbe_restart_dev\n");
|
||||
|
|
@ -1355,6 +1530,7 @@ static int xgbe_open(struct net_device *netdev)
|
|||
|
||||
INIT_WORK(&pdata->service_work, xgbe_service);
|
||||
INIT_WORK(&pdata->restart_work, xgbe_restart);
|
||||
INIT_WORK(&pdata->stopdev_work, xgbe_stopdev);
|
||||
INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
|
||||
xgbe_init_timers(pdata);
|
||||
|
||||
|
|
|
|||
|
|
@ -190,6 +190,7 @@ struct xgbe_prv_data *xgbe_alloc_pdata(struct device *dev)
|
|||
pdata->msg_enable = netif_msg_init(debug, default_msg_level);
|
||||
|
||||
set_bit(XGBE_DOWN, &pdata->dev_state);
|
||||
set_bit(XGBE_STOPPED, &pdata->dev_state);
|
||||
|
||||
return pdata;
|
||||
}
|
||||
|
|
@ -263,6 +264,14 @@ int xgbe_config_netdev(struct xgbe_prv_data *pdata)
|
|||
netdev->base_addr = (unsigned long)pdata->xgmac_regs;
|
||||
memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len);
|
||||
|
||||
/* Initialize ECC timestamps */
|
||||
pdata->tx_sec_period = jiffies;
|
||||
pdata->tx_ded_period = jiffies;
|
||||
pdata->rx_sec_period = jiffies;
|
||||
pdata->rx_ded_period = jiffies;
|
||||
pdata->desc_sec_period = jiffies;
|
||||
pdata->desc_ded_period = jiffies;
|
||||
|
||||
/* Issue software reset to device */
|
||||
pdata->hw_if.exit(pdata);
|
||||
|
||||
|
|
@ -384,6 +393,10 @@ int xgbe_config_netdev(struct xgbe_prv_data *pdata)
|
|||
snprintf(pdata->an_name, sizeof(pdata->an_name) - 1, "%s-pcs",
|
||||
netdev_name(netdev));
|
||||
|
||||
/* Create the ECC name based on netdev name */
|
||||
snprintf(pdata->ecc_name, sizeof(pdata->ecc_name) - 1, "%s-ecc",
|
||||
netdev_name(netdev));
|
||||
|
||||
/* Create workqueues */
|
||||
pdata->dev_workqueue =
|
||||
create_singlethread_workqueue(netdev_name(netdev));
|
||||
|
|
|
|||
|
|
@ -482,6 +482,7 @@ static const struct xgbe_version_data xgbe_v2a = {
|
|||
.tx_max_fifo_size = 229376,
|
||||
.rx_max_fifo_size = 229376,
|
||||
.tx_tstamp_workaround = 1,
|
||||
.ecc_support = 1,
|
||||
};
|
||||
|
||||
static const struct xgbe_version_data xgbe_v2b = {
|
||||
|
|
@ -491,6 +492,7 @@ static const struct xgbe_version_data xgbe_v2b = {
|
|||
.tx_max_fifo_size = 65536,
|
||||
.rx_max_fifo_size = 65536,
|
||||
.tx_tstamp_workaround = 1,
|
||||
.ecc_support = 1,
|
||||
};
|
||||
|
||||
static const struct pci_device_id xgbe_pci_table[] = {
|
||||
|
|
|
|||
|
|
@ -285,6 +285,9 @@
|
|||
#define XGBE_SGMII_AN_LINK_SPEED_1000 0x08
|
||||
#define XGBE_SGMII_AN_LINK_DUPLEX BIT(4)
|
||||
|
||||
/* ECC correctable error notification window (seconds) */
|
||||
#define XGBE_ECC_LIMIT 60
|
||||
|
||||
struct xgbe_prv_data;
|
||||
|
||||
struct xgbe_packet_data {
|
||||
|
|
@ -461,6 +464,7 @@ enum xgbe_state {
|
|||
XGBE_DOWN,
|
||||
XGBE_LINK_INIT,
|
||||
XGBE_LINK_ERR,
|
||||
XGBE_STOPPED,
|
||||
};
|
||||
|
||||
enum xgbe_int {
|
||||
|
|
@ -480,6 +484,12 @@ enum xgbe_int_state {
|
|||
XGMAC_INT_STATE_RESTORE,
|
||||
};
|
||||
|
||||
enum xgbe_ecc_sec {
|
||||
XGBE_ECC_SEC_TX,
|
||||
XGBE_ECC_SEC_RX,
|
||||
XGBE_ECC_SEC_DESC,
|
||||
};
|
||||
|
||||
enum xgbe_speed {
|
||||
XGBE_SPEED_1000 = 0,
|
||||
XGBE_SPEED_2500,
|
||||
|
|
@ -694,6 +704,10 @@ struct xgbe_hw_if {
|
|||
int (*disable_rss)(struct xgbe_prv_data *);
|
||||
int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
|
||||
int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
|
||||
|
||||
/* For ECC */
|
||||
void (*disable_ecc_ded)(struct xgbe_prv_data *);
|
||||
void (*disable_ecc_sec)(struct xgbe_prv_data *, enum xgbe_ecc_sec);
|
||||
};
|
||||
|
||||
/* This structure represents implementation specific routines for an
|
||||
|
|
@ -827,6 +841,7 @@ struct xgbe_version_data {
|
|||
unsigned int tx_max_fifo_size;
|
||||
unsigned int rx_max_fifo_size;
|
||||
unsigned int tx_tstamp_workaround;
|
||||
unsigned int ecc_support;
|
||||
};
|
||||
|
||||
struct xgbe_prv_data {
|
||||
|
|
@ -868,6 +883,21 @@ struct xgbe_prv_data {
|
|||
/* Flags representing xgbe_state */
|
||||
unsigned long dev_state;
|
||||
|
||||
/* ECC support */
|
||||
unsigned long tx_sec_period;
|
||||
unsigned long tx_ded_period;
|
||||
unsigned long rx_sec_period;
|
||||
unsigned long rx_ded_period;
|
||||
unsigned long desc_sec_period;
|
||||
unsigned long desc_ded_period;
|
||||
|
||||
unsigned int tx_sec_count;
|
||||
unsigned int tx_ded_count;
|
||||
unsigned int rx_sec_count;
|
||||
unsigned int rx_ded_count;
|
||||
unsigned int desc_ded_count;
|
||||
unsigned int desc_sec_count;
|
||||
|
||||
struct msix_entry *msix_entries;
|
||||
int dev_irq;
|
||||
int ecc_irq;
|
||||
|
|
@ -880,6 +910,8 @@ struct xgbe_prv_data {
|
|||
unsigned int channel_irq_count;
|
||||
unsigned int channel_irq_mode;
|
||||
|
||||
char ecc_name[IFNAMSIZ + 32];
|
||||
|
||||
struct xgbe_hw_if hw_if;
|
||||
struct xgbe_phy_if phy_if;
|
||||
struct xgbe_desc_if desc_if;
|
||||
|
|
@ -990,8 +1022,9 @@ struct xgbe_prv_data {
|
|||
/* Hardware features of the device */
|
||||
struct xgbe_hw_features hw_feat;
|
||||
|
||||
/* Device restart work structure */
|
||||
/* Device work structures */
|
||||
struct work_struct restart_work;
|
||||
struct work_struct stopdev_work;
|
||||
|
||||
/* Keeps track of power mode */
|
||||
unsigned int power_down;
|
||||
|
|
|
|||
Loading…
Reference in a new issue