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clk: meson: axg: add MIPI DSI Host clock
This adds the MIPI DSI Host clock, used to measure the signal timings (ENC VSYNC or DW-MIPI-DSI eDPI timings). Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200915124553.8056-5-narmstrong@baylibre.com
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14ebb3154b
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2 changed files with 69 additions and 1 deletions
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@ -1703,6 +1703,66 @@ static struct clk_regmap axg_cts_encl = {
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},
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},
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};
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};
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/* MIPI DSI Host Clock */
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static u32 mux_table_axg_vdin_meas[] = { 0, 1, 2, 3, 6, 7 };
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static const struct clk_parent_data axg_vdin_meas_parent_data[] = {
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{ .fw_name = "xtal", },
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{ .hw = &axg_fclk_div4.hw },
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{ .hw = &axg_fclk_div3.hw },
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{ .hw = &axg_fclk_div5.hw },
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{ .hw = &axg_fclk_div2.hw },
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{ .hw = &axg_fclk_div7.hw },
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};
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static struct clk_regmap axg_vdin_meas_sel = {
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.data = &(struct clk_regmap_mux_data){
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.offset = HHI_VDIN_MEAS_CLK_CNTL,
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.mask = 0x7,
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.shift = 21,
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.flags = CLK_MUX_ROUND_CLOSEST,
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.table = mux_table_axg_vdin_meas,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdin_meas_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_data = axg_vdin_meas_parent_data,
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.num_parents = ARRAY_SIZE(axg_vdin_meas_parent_data),
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap axg_vdin_meas_div = {
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.data = &(struct clk_regmap_div_data){
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.offset = HHI_VDIN_MEAS_CLK_CNTL,
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.shift = 12,
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.width = 7,
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},
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.hw.init = &(struct clk_init_data){
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.name = "vdin_meas_div",
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.ops = &clk_regmap_divider_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&axg_vdin_meas_sel.hw },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static struct clk_regmap axg_vdin_meas = {
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.data = &(struct clk_regmap_gate_data){
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.offset = HHI_VDIN_MEAS_CLK_CNTL,
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.bit_idx = 20,
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},
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.hw.init = &(struct clk_init_data) {
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.name = "vdin_meas",
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.ops = &clk_regmap_gate_ops,
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.parent_hws = (const struct clk_hw *[]) {
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&axg_vdin_meas_div.hw },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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};
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static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
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static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
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9, 10, 11, 13, 14, };
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9, 10, 11, 13, 14, };
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static const struct clk_parent_data gen_clk_parent_data[] = {
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static const struct clk_parent_data gen_clk_parent_data[] = {
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@ -1966,6 +2026,9 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
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[CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw,
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[CLKID_VCLK2_DIV12] = &axg_vclk2_div12.hw,
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[CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw,
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[CLKID_CTS_ENCL_SEL] = &axg_cts_encl_sel.hw,
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[CLKID_CTS_ENCL] = &axg_cts_encl.hw,
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[CLKID_CTS_ENCL] = &axg_cts_encl.hw,
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[CLKID_VDIN_MEAS_SEL] = &axg_vdin_meas_sel.hw,
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[CLKID_VDIN_MEAS_DIV] = &axg_vdin_meas_div.hw,
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[CLKID_VDIN_MEAS] = &axg_vdin_meas.hw,
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[NR_CLKS] = NULL,
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[NR_CLKS] = NULL,
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},
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},
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.num = NR_CLKS,
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.num = NR_CLKS,
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@ -2094,6 +2157,9 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
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&axg_vclk2_div12_en,
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&axg_vclk2_div12_en,
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&axg_cts_encl_sel,
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&axg_cts_encl_sel,
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&axg_cts_encl,
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&axg_cts_encl,
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&axg_vdin_meas_sel,
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&axg_vdin_meas_div,
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&axg_vdin_meas,
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};
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};
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static const struct meson_eeclkc_data axg_clkc_data = {
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static const struct meson_eeclkc_data axg_clkc_data = {
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@ -158,8 +158,10 @@
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#define CLKID_VCLK2_DIV6_EN 120
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#define CLKID_VCLK2_DIV6_EN 120
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#define CLKID_VCLK2_DIV12_EN 121
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#define CLKID_VCLK2_DIV12_EN 121
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#define CLKID_CTS_ENCL_SEL 132
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#define CLKID_CTS_ENCL_SEL 132
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#define CLKID_VDIN_MEAS_SEL 134
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#define CLKID_VDIN_MEAS_DIV 135
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#define NR_CLKS 134
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#define NR_CLKS 137
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/* include the CLKIDs that have been made part of the DT binding */
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/* include the CLKIDs that have been made part of the DT binding */
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#include <dt-bindings/clock/axg-clkc.h>
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#include <dt-bindings/clock/axg-clkc.h>
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