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drm: msm: a6xx: Add support for A618
This patch adds support for enabling Graphics Bus Interface(GBIF) used in multiple A6xx series chipets. Also makes changes to the PDC/RSC sequencing specifically required for A618. This is needed for proper interfacing with RPMH. Signed-off-by: Sharat Masetty <smasetty@codeaurora.org> Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Sharat Masetty
Rob Clark
parent
358ffda520
commit
e812744c5f
5 changed files with 154 additions and 13 deletions
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@ -16,11 +16,11 @@ The rules-ng-ng source files this header was generated from are:
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- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
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- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-12-02 17:29:54)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 140790 bytes, from 2018-12-02 17:29:54)
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- /home/smasetty/playarea/envytools/rnndb/adreno/a6xx.xml ( 161969 bytes, from 2019-11-29 07:18:16)
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- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
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- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
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Copyright (C) 2013-2018 by the following authors:
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Copyright (C) 2013-2019 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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@ -2519,6 +2519,54 @@ static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val)
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#define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
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#define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02
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#define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03
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#define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04
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#define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05
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#define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06
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#define REG_A6XX_GBIF_HALT 0x00003c45
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#define REG_A6XX_GBIF_HALT_ACK 0x00003c46
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#define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0
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#define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2
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#define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3
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#define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4
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#define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5
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#define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6
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#define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7
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#define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8
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#define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9
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#define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca
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#define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb
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#define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc
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#define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd
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#define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce
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#define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf
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#define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0
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#define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1
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#define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4
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#define A6XX_RB_WINDOW_OFFSET2_WINDOW_OFFSET_DISABLE 0x80000000
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#define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00007fff
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@ -1,5 +1,5 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */
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/* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
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#include <linux/clk.h>
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#include <linux/interconnect.h>
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@ -435,6 +435,8 @@ static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
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static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
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{
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struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
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struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
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struct platform_device *pdev = to_platform_device(gmu->dev);
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void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
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void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
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@ -482,20 +484,34 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080);
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if (adreno_is_a618(adreno_gpu))
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30090);
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else
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
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if (adreno_is_a618(adreno_gpu))
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
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else
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080);
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if (adreno_is_a618(adreno_gpu))
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30090);
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else
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080);
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pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
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/* Setup GPU PDC */
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@ -1,5 +1,5 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. */
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/* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
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#include "msm_gem.h"
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@ -378,6 +378,18 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
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struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
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int ret;
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/*
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* During a previous slumber, GBIF halt is asserted to ensure
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* no further transaction can go through GPU before GPU
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* headswitch is turned off.
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*
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* This halt is deasserted once headswitch goes off but
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* incase headswitch doesn't goes off clear GBIF halt
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* here to ensure GPU wake-up doesn't fail because of
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* halted GPU transactions.
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*/
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gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
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/* Make sure the GMU keeps the GPU on while we set it up */
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a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
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@ -406,12 +418,17 @@ static int a6xx_hw_init(struct msm_gpu *gpu)
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gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);
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gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
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/* enable hardware clockgating */
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a6xx_set_hwcg(gpu, true);
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/*
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* enable hardware clockgating
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* For now enable clock gating only for a630
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*/
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if (adreno_is_a630(adreno_gpu))
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a6xx_set_hwcg(gpu, true);
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/* VBIF start */
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gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
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/* VBIF/GBIF start*/
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gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
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if (adreno_is_a630(adreno_gpu))
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gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
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/* Make all blocks contribute to the GPU BUSY perf counter */
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gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
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@ -731,6 +748,39 @@ static const u32 a6xx_register_offsets[REG_ADRENO_REGISTER_MAX] = {
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REG_ADRENO_DEFINE(REG_ADRENO_CP_RB_CNTL, REG_A6XX_CP_RB_CNTL),
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};
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#define GBIF_CLIENT_HALT_MASK BIT(0)
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#define GBIF_ARB_HALT_MASK BIT(1)
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static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu)
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{
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struct msm_gpu *gpu = &adreno_gpu->base;
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if(!a6xx_has_gbif(adreno_gpu)){
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gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
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spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
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0xf) == 0xf);
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gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
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return;
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}
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/* Halt new client requests on GBIF */
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gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
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spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
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(GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
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/* Halt all AXI requests on GBIF */
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gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
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spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
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(GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
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/*
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* GMU needs DDR access in slumber path. Deassert GBIF halt now
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* to allow for GMU to access system memory.
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*/
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gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
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}
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static int a6xx_pm_resume(struct msm_gpu *gpu)
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{
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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@ -755,6 +805,16 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu)
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devfreq_suspend_device(gpu->devfreq.devfreq);
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/*
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* Make sure the GMU is idle before continuing (because some transitions
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* may use VBIF
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*/
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a6xx_gmu_wait_for_idle(&a6xx_gpu->gmu);
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/* Clear the VBIF pipe before shutting down */
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/* FIXME: This accesses the GPU - do we need to make sure it is on? */
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a6xx_bus_clear_pending_transactions(adreno_gpu);
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return a6xx_gmu_stop(a6xx_gpu);
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}
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@ -1,5 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2017 The Linux Foundation. All rights reserved. */
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/* Copyright (c) 2017, 2019 The Linux Foundation. All rights reserved. */
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#ifndef __A6XX_GPU_H__
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#define __A6XX_GPU_H__
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@ -42,6 +42,13 @@ struct a6xx_gpu {
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#define A6XX_PROTECT_RDONLY(_reg, _len) \
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((((_len) & 0x3FFF) << 18) | ((_reg) & 0x3FFFF))
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static inline bool a6xx_has_gbif(struct adreno_gpu *gpu)
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{
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if(adreno_is_a630(gpu))
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return false;
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return true;
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}
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int a6xx_gmu_resume(struct a6xx_gpu *gpu);
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int a6xx_gmu_stop(struct a6xx_gpu *gpu);
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@ -3,7 +3,7 @@
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
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* Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
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*/
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#ifndef __ADRENO_GPU_H__
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@ -227,6 +227,16 @@ static inline int adreno_is_a540(struct adreno_gpu *gpu)
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return gpu->revn == 540;
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}
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static inline int adreno_is_a618(struct adreno_gpu *gpu)
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{
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return gpu->revn == 618;
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}
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static inline int adreno_is_a630(struct adreno_gpu *gpu)
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{
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return gpu->revn == 630;
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}
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int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
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const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
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const char *fwname);
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