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ARM: pm: preallocate a page table for suspend/resume
Preallocate a page table and setup an identity mapping for the MMU enable code. This means we don't have to "borrow" a page table to do this, avoiding complexities with L2 cache coherency. Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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parent
f5fa68d967
commit
e8ce0eb5e2
11 changed files with 62 additions and 72 deletions
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@ -1,22 +1,7 @@
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#ifndef __ASM_ARM_SUSPEND_H
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#define __ASM_ARM_SUSPEND_H
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#include <asm/memory.h>
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#include <asm/tlbflush.h>
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extern void cpu_resume(void);
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/*
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* Hide the first two arguments to __cpu_suspend - these are an implementation
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* detail which platform code shouldn't have to know about.
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*/
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static inline int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
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{
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extern int __cpu_suspend(int, long, unsigned long,
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int (*)(unsigned long));
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int ret = __cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn);
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flush_tlb_all();
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return ret;
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}
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extern int cpu_suspend(unsigned long, int (*)(unsigned long));
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#endif
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@ -29,7 +29,7 @@ obj-$(CONFIG_MODULES) += armksyms.o module.o
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obj-$(CONFIG_ARTHUR) += arthur.o
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obj-$(CONFIG_ISA_DMA) += dma-isa.o
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obj-$(CONFIG_PCI) += bios32.o isa.o
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obj-$(CONFIG_PM_SLEEP) += sleep.o
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obj-$(CONFIG_PM_SLEEP) += sleep.o suspend.o
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obj-$(CONFIG_HAVE_SCHED_CLOCK) += sched_clock.o
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obj-$(CONFIG_SMP) += smp.o smp_tlb.o
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obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o
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@ -27,7 +27,7 @@ ENTRY(__cpu_suspend)
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sub sp, sp, r5 @ allocate CPU state on stack
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mov r0, sp @ save pointer to CPU save block
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add ip, ip, r1 @ convert resume fn to phys
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stmfd sp!, {r1, r6, ip} @ save v:p, virt SP, phys resume fn
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stmfd sp!, {r6, ip} @ save virt SP, phys resume fn
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ldr r5, =sleep_save_sp
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add r6, sp, r1 @ convert SP to phys
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stmfd sp!, {r2, r3} @ save suspend func arg and pointer
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@ -60,7 +60,7 @@ ENDPROC(__cpu_suspend)
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.ltorg
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cpu_suspend_abort:
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ldmia sp!, {r1 - r3} @ pop v:p, virt SP, phys resume fn
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ldmia sp!, {r2 - r3} @ pop virt SP, phys resume fn
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teq r0, #0
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moveq r0, #1 @ force non-zero value
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mov sp, r2
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@ -74,28 +74,19 @@ ENDPROC(cpu_suspend_abort)
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* r3 = L1 section flags
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*/
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ENTRY(cpu_resume_mmu)
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adr r4, cpu_resume_turn_mmu_on
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mov r4, r4, lsr #20
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orr r3, r3, r4, lsl #20
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ldr r5, [r2, r4, lsl #2] @ save old mapping
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str r3, [r2, r4, lsl #2] @ setup 1:1 mapping for mmu code
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sub r2, r2, r1
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ldr r3, =cpu_resume_after_mmu
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bic r1, r0, #CR_C @ ensure D-cache is disabled
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b cpu_resume_turn_mmu_on
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ENDPROC(cpu_resume_mmu)
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.ltorg
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.align 5
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cpu_resume_turn_mmu_on:
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mcr p15, 0, r1, c1, c0, 0 @ turn on MMU, I-cache, etc
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mrc p15, 0, r1, c0, c0, 0 @ read id reg
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mov r1, r1
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mov r1, r1
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ENTRY(cpu_resume_turn_mmu_on)
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mcr p15, 0, r0, c1, c0, 0 @ turn on MMU, I-cache, etc
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mrc p15, 0, r0, c0, c0, 0 @ read id reg
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mov r0, r0
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mov r0, r0
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mov pc, r3 @ jump to virtual address
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ENDPROC(cpu_resume_turn_mmu_on)
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cpu_resume_after_mmu:
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str r5, [r2, r4, lsl #2] @ restore old mapping
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mcr p15, 0, r0, c1, c0, 0 @ turn on D-cache
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bl cpu_init @ restore the und/abt/irq banked regs
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mov r0, #0 @ return zero on success
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ldmfd sp!, {r4 - r11, pc}
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@ -121,11 +112,11 @@ ENTRY(cpu_resume)
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ldr r0, sleep_save_sp @ stack phys addr
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#endif
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setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off
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@ load v:p, stack, resume fn
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ARM( ldmia r0!, {r1, sp, pc} )
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THUMB( ldmia r0!, {r1, r2, r3} )
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THUMB( mov sp, r2 )
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THUMB( bx r3 )
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@ load stack, resume fn
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ARM( ldmia r0!, {sp, pc} )
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THUMB( ldmia r0!, {r2, r3} )
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THUMB( mov sp, r2 )
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THUMB( bx r3 )
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ENDPROC(cpu_resume)
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sleep_save_sp:
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48
arch/arm/kernel/suspend.c
Normal file
48
arch/arm/kernel/suspend.c
Normal file
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@ -0,0 +1,48 @@
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#include <linux/init.h>
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#include <asm/pgalloc.h>
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#include <asm/pgtable.h>
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#include <asm/memory.h>
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#include <asm/suspend.h>
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#include <asm/tlbflush.h>
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static pgd_t *suspend_pgd;
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extern int __cpu_suspend(int, long, unsigned long, int (*)(unsigned long));
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extern void cpu_resume_turn_mmu_on(void);
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/*
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* Hide the first two arguments to __cpu_suspend - these are an implementation
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* detail which platform code shouldn't have to know about.
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*/
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int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
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{
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struct mm_struct *mm = current->active_mm;
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int ret;
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if (!suspend_pgd)
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return -EINVAL;
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/*
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* Temporarily switch the page tables to our suspend page
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* tables, which contain the temporary identity mapping
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* required for resuming.
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*/
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cpu_switch_mm(suspend_pgd, mm);
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ret = __cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn);
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cpu_switch_mm(mm->pgd, mm);
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local_flush_tlb_all();
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return ret;
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}
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static int __init cpu_suspend_init(void)
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{
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suspend_pgd = pgd_alloc(&init_mm);
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if (suspend_pgd) {
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unsigned long addr = virt_to_phys(cpu_resume_turn_mmu_on);
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identity_mapping_add(suspend_pgd, addr, addr + SECTION_SIZE);
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}
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return suspend_pgd ? 0 : -ENOMEM;
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}
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core_initcall(cpu_suspend_init);
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@ -400,10 +400,6 @@ ENTRY(cpu_arm920_do_resume)
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mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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mcr p15, 0, r6, c2, c0, 0 @ TTB address
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mov r0, r7 @ control register
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mov r2, r6, lsr #14 @ get TTB0 base
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mov r2, r2, lsl #14
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ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE
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b cpu_resume_mmu
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ENDPROC(cpu_arm920_do_resume)
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#endif
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@ -415,10 +415,6 @@ ENTRY(cpu_arm926_do_resume)
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mcr p15, 0, r5, c3, c0, 0 @ Domain ID
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mcr p15, 0, r6, c2, c0, 0 @ TTB address
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mov r0, r7 @ control register
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mov r2, r6, lsr #14 @ get TTB0 base
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mov r2, r2, lsl #14
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ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE
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b cpu_resume_mmu
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ENDPROC(cpu_arm926_do_resume)
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#endif
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@ -192,10 +192,6 @@ ENTRY(cpu_sa1100_do_resume)
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mcr p15, 0, r5, c2, c0, 0 @ translation table base addr
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mcr p15, 0, r6, c13, c0, 0 @ PID
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mov r0, r7 @ control register
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mov r2, r5, lsr #14 @ get TTB0 base
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mov r2, r2, lsl #14
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ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE
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b cpu_resume_mmu
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ENDPROC(cpu_sa1100_do_resume)
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#endif
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@ -161,14 +161,8 @@ ENTRY(cpu_v6_do_resume)
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mcr p15, 0, ip, c2, c0, 2 @ TTB control register
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mcr p15, 0, ip, c7, c5, 4 @ ISB
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mov r0, r11 @ control register
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mov r2, r7, lsr #14 @ get TTB0 base
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mov r2, r2, lsl #14
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ldr r3, cpu_resume_l1_flags
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b cpu_resume_mmu
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ENDPROC(cpu_v6_do_resume)
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cpu_resume_l1_flags:
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ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
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ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
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#endif
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string cpu_v6_name, "ARMv6-compatible processor"
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@ -259,14 +259,8 @@ ENTRY(cpu_v7_do_resume)
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isb
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dsb
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mov r0, r9 @ control register
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mov r2, r7, lsr #14 @ get TTB0 base
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mov r2, r2, lsl #14
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ldr r3, cpu_resume_l1_flags
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b cpu_resume_mmu
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ENDPROC(cpu_v7_do_resume)
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cpu_resume_l1_flags:
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ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
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ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
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#endif
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__CPUINIT
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@ -435,13 +435,7 @@ ENTRY(cpu_xsc3_do_resume)
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mcr p15, 0, r7, c3, c0, 0 @ domain ID
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mcr p15, 0, r8, c2, c0, 0 @ translation table base addr
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mcr p15, 0, r9, c1, c0, 1 @ auxiliary control reg
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@ temporarily map resume_turn_on_mmu into the page table,
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@ otherwise prefetch abort occurs after MMU is turned on
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mov r0, r10 @ control register
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mov r2, r8, lsr #14 @ get TTB0 base
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mov r2, r2, lsl #14
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ldr r3, =0x542e @ section flags
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b cpu_resume_mmu
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ENDPROC(cpu_xsc3_do_resume)
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#endif
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@ -548,10 +548,6 @@ ENTRY(cpu_xscale_do_resume)
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mcr p15, 0, r8, c2, c0, 0 @ translation table base addr
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mcr p15, 0, r9, c1, c1, 0 @ auxiliary control reg
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mov r0, r10 @ control register
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mov r2, r8, lsr #14 @ get TTB0 base
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mov r2, r2, lsl #14
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ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
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PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE
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b cpu_resume_mmu
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ENDPROC(cpu_xscale_do_resume)
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#endif
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