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clk: renesas: r8a779g0: Fix HSCIF parent clocks
[ Upstream commita9003f74f5
] As serial communication requires a clean clock signal, the High Speed Serial Communication Interfaces with FIFO (HSCIF) is clocked by a clock that is not affected by Spread Spectrum or Fractional Multiplication. Hence change the parent clocks for the HSCIF modules from the S0D3_PER clock to the SASYNCPERD1 clock (which has the same clock rate), cfr. R-Car V4H Hardware User's Manual rev. 0.54. Fixes:0ab55cf183
("clk: renesas: cpg-mssr: Add support for R-Car V4H") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/b7928abc8b9f53d5b06ec8624342f449de3d24ec.1665147497.git.geert+renesas@glider.be Signed-off-by: Sasha Levin <sashal@kernel.org>
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1 changed files with 4 additions and 4 deletions
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@ -150,10 +150,10 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
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};
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static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
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DEF_MOD("hscif0", 514, R8A779G0_CLK_S0D3_PER),
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DEF_MOD("hscif1", 515, R8A779G0_CLK_S0D3_PER),
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DEF_MOD("hscif2", 516, R8A779G0_CLK_S0D3_PER),
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DEF_MOD("hscif3", 517, R8A779G0_CLK_S0D3_PER),
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DEF_MOD("hscif0", 514, R8A779G0_CLK_SASYNCPERD1),
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DEF_MOD("hscif1", 515, R8A779G0_CLK_SASYNCPERD1),
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DEF_MOD("hscif2", 516, R8A779G0_CLK_SASYNCPERD1),
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DEF_MOD("hscif3", 517, R8A779G0_CLK_SASYNCPERD1),
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};
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/*
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