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staging: octeon: support enabling multiple rx groups
Support enabling multiple RX groups. Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
942bab48e6
commit
e971a119f7
3 changed files with 77 additions and 49 deletions
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@ -47,7 +47,7 @@ static struct oct_rx_group {
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int irq;
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int group;
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struct napi_struct napi;
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} oct_rx_group;
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} oct_rx_group[16];
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/**
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* cvm_oct_do_interrupt - interrupt handler.
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@ -442,7 +442,16 @@ static int cvm_oct_napi_poll(struct napi_struct *napi, int budget)
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*/
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void cvm_oct_poll_controller(struct net_device *dev)
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{
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cvm_oct_poll(&oct_rx_group, 16);
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int i;
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for (i = 0; i < ARRAY_SIZE(oct_rx_group); i++) {
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if (!(pow_receive_groups & BIT(i)))
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continue;
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cvm_oct_poll(&oct_rx_group[i], 16);
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}
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}
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#endif
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@ -461,65 +470,80 @@ void cvm_oct_rx_initialize(void)
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if (!dev_for_napi)
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panic("No net_devices were allocated.");
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netif_napi_add(dev_for_napi, &oct_rx_group.napi, cvm_oct_napi_poll,
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rx_napi_weight);
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napi_enable(&oct_rx_group.napi);
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for (i = 0; i < ARRAY_SIZE(oct_rx_group); i++) {
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int ret;
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oct_rx_group.irq = OCTEON_IRQ_WORKQ0 + pow_receive_group;
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oct_rx_group.group = pow_receive_group;
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if (!(pow_receive_groups & BIT(i)))
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continue;
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/* Register an IRQ handler to receive POW interrupts */
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i = request_irq(oct_rx_group.irq, cvm_oct_do_interrupt, 0, "Ethernet",
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&oct_rx_group.napi);
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netif_napi_add(dev_for_napi, &oct_rx_group[i].napi,
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cvm_oct_napi_poll, rx_napi_weight);
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napi_enable(&oct_rx_group[i].napi);
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if (i)
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panic("Could not acquire Ethernet IRQ %d\n", oct_rx_group.irq);
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oct_rx_group[i].irq = OCTEON_IRQ_WORKQ0 + i;
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oct_rx_group[i].group = i;
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disable_irq_nosync(oct_rx_group.irq);
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/* Register an IRQ handler to receive POW interrupts */
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ret = request_irq(oct_rx_group[i].irq, cvm_oct_do_interrupt, 0,
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"Ethernet", &oct_rx_group[i].napi);
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if (ret)
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panic("Could not acquire Ethernet IRQ %d\n",
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oct_rx_group[i].irq);
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/* Enable POW interrupt when our port has at least one packet */
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if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
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union cvmx_sso_wq_int_thrx int_thr;
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union cvmx_pow_wq_int_pc int_pc;
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disable_irq_nosync(oct_rx_group[i].irq);
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int_thr.u64 = 0;
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int_thr.s.tc_en = 1;
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int_thr.s.tc_thr = 1;
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cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(pow_receive_group),
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int_thr.u64);
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/* Enable POW interrupt when our port has at least one packet */
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if (OCTEON_IS_MODEL(OCTEON_CN68XX)) {
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union cvmx_sso_wq_int_thrx int_thr;
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union cvmx_pow_wq_int_pc int_pc;
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int_pc.u64 = 0;
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int_pc.s.pc_thr = 5;
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cvmx_write_csr(CVMX_SSO_WQ_INT_PC, int_pc.u64);
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} else {
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union cvmx_pow_wq_int_thrx int_thr;
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union cvmx_pow_wq_int_pc int_pc;
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int_thr.u64 = 0;
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int_thr.s.tc_en = 1;
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int_thr.s.tc_thr = 1;
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cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(i), int_thr.u64);
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int_thr.u64 = 0;
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int_thr.s.tc_en = 1;
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int_thr.s.tc_thr = 1;
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cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group),
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int_thr.u64);
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int_pc.u64 = 0;
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int_pc.s.pc_thr = 5;
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cvmx_write_csr(CVMX_SSO_WQ_INT_PC, int_pc.u64);
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} else {
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union cvmx_pow_wq_int_thrx int_thr;
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union cvmx_pow_wq_int_pc int_pc;
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int_pc.u64 = 0;
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int_pc.s.pc_thr = 5;
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cvmx_write_csr(CVMX_POW_WQ_INT_PC, int_pc.u64);
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int_thr.u64 = 0;
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int_thr.s.tc_en = 1;
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int_thr.s.tc_thr = 1;
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cvmx_write_csr(CVMX_POW_WQ_INT_THRX(i), int_thr.u64);
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int_pc.u64 = 0;
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int_pc.s.pc_thr = 5;
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cvmx_write_csr(CVMX_POW_WQ_INT_PC, int_pc.u64);
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}
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/* Schedule NAPI now. This will indirectly enable the
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* interrupt.
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*/
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napi_schedule(&oct_rx_group[i].napi);
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}
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/* Schedule NAPI now. This will indirectly enable the interrupt. */
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napi_schedule(&oct_rx_group.napi);
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}
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void cvm_oct_rx_shutdown(void)
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{
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/* Disable POW interrupt */
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if (OCTEON_IS_MODEL(OCTEON_CN68XX))
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cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(pow_receive_group), 0);
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else
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cvmx_write_csr(CVMX_POW_WQ_INT_THRX(pow_receive_group), 0);
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int i;
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/* Free the interrupt handler */
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free_irq(oct_rx_group.irq, cvm_oct_device);
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for (i = 0; i < ARRAY_SIZE(oct_rx_group); i++) {
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netif_napi_del(&oct_rx_group.napi);
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if (!(pow_receive_groups & BIT(i)))
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continue;
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/* Disable POW interrupt */
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if (OCTEON_IS_MODEL(OCTEON_CN68XX))
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cvmx_write_csr(CVMX_SSO_WQ_INT_THRX(i), 0);
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else
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cvmx_write_csr(CVMX_POW_WQ_INT_THRX(i), 0);
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/* Free the interrupt handler */
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free_irq(oct_rx_group[i].irq, cvm_oct_device);
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netif_napi_del(&oct_rx_group[i].napi);
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}
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}
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@ -45,7 +45,7 @@ MODULE_PARM_DESC(num_packet_buffers, "\n"
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"\tNumber of packet buffers to allocate and store in the\n"
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"\tFPA. By default, 1024 packet buffers are used.\n");
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int pow_receive_group = 15;
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static int pow_receive_group = 15;
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module_param(pow_receive_group, int, 0444);
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MODULE_PARM_DESC(pow_receive_group, "\n"
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"\tPOW group to receive packets from. All ethernet hardware\n"
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@ -86,6 +86,8 @@ int rx_napi_weight = 32;
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module_param(rx_napi_weight, int, 0444);
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MODULE_PARM_DESC(rx_napi_weight, "The NAPI WEIGHT parameter.");
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/* Mask indicating which receive groups are in use. */
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int pow_receive_groups;
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/*
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* cvm_oct_poll_queue_stopping - flag to indicate polling should stop.
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@ -678,6 +680,8 @@ static int cvm_oct_probe(struct platform_device *pdev)
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cvmx_helper_initialize_packet_io_global();
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pow_receive_groups = BIT(pow_receive_group);
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/* Change the input group for all ports before input is enabled */
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num_interfaces = cvmx_helper_get_number_of_interfaces();
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for (interface = 0; interface < num_interfaces; interface++) {
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@ -72,7 +72,7 @@ void cvm_oct_link_poll(struct net_device *dev);
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extern int always_use_pow;
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extern int pow_send_group;
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extern int pow_receive_group;
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extern int pow_receive_groups;
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extern char pow_send_list[];
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extern struct net_device *cvm_oct_device[];
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extern atomic_t cvm_oct_poll_queue_stopping;
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