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pinctrl: renesas: r8a77995: Add bias pinconf support
Implement support for pull-up (most pins, excl. DU_DOTCLKIN0) and pull-down (most pins, excl. JTAG) handling for the R-Car D3 SoC, using some parts from the common R-Car bias handling, which requires making rcar_pin_to_bias_reg() public. R-Car D3 needs special handling for the NFRE# (GP_3_0) and NFWE# (GP_3_1) pins. Unlike all other pins, they are controlled by different bits in the LSI pin pull-up/down control register (PUD2) than in the LSI pin pull-enable register (PUEN2). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/04aad2b0bf82a32fb08e5e21e4ac1fb03452724f.1625064076.git.geert+renesas@glider.be
This commit is contained in:
Geert Uytterhoeven
parent
7ebaa41047
commit
e9d66bdbc5
3 changed files with 316 additions and 9 deletions
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@ -14,16 +14,27 @@
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include "core.h"
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#include "sh_pfc.h"
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#define CPU_ALL_GP(fn, sfx) \
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PORT_GP_9(0, fn, sfx), \
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PORT_GP_32(1, fn, sfx), \
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PORT_GP_32(2, fn, sfx), \
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PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
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PORT_GP_32(4, fn, sfx), \
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PORT_GP_21(5, fn, sfx), \
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PORT_GP_14(6, fn, sfx)
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#define CPU_ALL_GP(fn, sfx) \
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PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE | SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN)
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#define CPU_ALL_NOGP(fn) \
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PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, SH_PFC_PIN_CFG_PULL_DOWN), \
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PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
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PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
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PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
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PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
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PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP)
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/*
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* F_() : just information
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@ -930,8 +941,17 @@ static const u16 pinmux_data[] = {
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PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A),
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};
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/*
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* Pins not associated with a GPIO port.
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*/
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enum {
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GP_ASSIGN_LAST(),
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NOGP_ALL(),
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};
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static const struct sh_pfc_pin pinmux_pins[] = {
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PINMUX_GPIO_GP_ALL(),
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PINMUX_NOGP_ALL(),
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};
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/* - AUDIO CLOCK ------------------------------------------------------------- */
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@ -2834,6 +2854,214 @@ static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *po
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return bit;
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}
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static const struct pinmux_bias_reg pinmux_bias_regs[] = {
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{ PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
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[ 0] = RCAR_GP_PIN(1, 9), /* DU_DG1 */
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[ 1] = RCAR_GP_PIN(1, 8), /* DU_DG0 */
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[ 2] = RCAR_GP_PIN(1, 7), /* DU_DB7 */
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[ 3] = RCAR_GP_PIN(1, 6), /* DU_DB6 */
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[ 4] = RCAR_GP_PIN(1, 5), /* DU_DB5 */
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[ 5] = RCAR_GP_PIN(1, 4), /* DU_DB4 */
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[ 6] = RCAR_GP_PIN(1, 3), /* DU_DB3 */
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[ 7] = RCAR_GP_PIN(1, 2), /* DU_DB2 */
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[ 8] = RCAR_GP_PIN(1, 1), /* DU_DB1 */
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[ 9] = RCAR_GP_PIN(1, 0), /* DU_DB0 */
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[10] = PIN_MLB_REF, /* MLB_REF */
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[11] = RCAR_GP_PIN(0, 8), /* MLB_SIG */
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[12] = RCAR_GP_PIN(0, 7), /* MLB_DAT */
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[13] = RCAR_GP_PIN(0, 6), /* MLB_CLK */
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[14] = RCAR_GP_PIN(0, 5), /* MSIOF2_RXD */
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[15] = RCAR_GP_PIN(0, 4), /* MSIOF2_TXD */
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[16] = RCAR_GP_PIN(0, 3), /* MSIOF2_SCK */
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[17] = RCAR_GP_PIN(0, 2), /* IRQ0_A */
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[18] = RCAR_GP_PIN(0, 1), /* USB0_OVC */
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[19] = RCAR_GP_PIN(0, 0), /* USB0_PWEN */
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[20] = PIN_PRESETOUT_N, /* PRESETOUT# */
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[21] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
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[22] = PIN_FSCLKST_N, /* FSCLKST# */
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[23] = SH_PFC_PIN_NONE,
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[24] = SH_PFC_PIN_NONE,
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[25] = SH_PFC_PIN_NONE,
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[26] = SH_PFC_PIN_NONE,
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[27] = SH_PFC_PIN_NONE,
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[28] = PIN_TDI, /* TDI */
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[29] = PIN_TMS, /* TMS */
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[30] = PIN_TCK, /* TCK */
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[31] = PIN_TRST_N, /* TRST# */
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} },
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{ PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
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[ 0] = RCAR_GP_PIN(2, 9), /* VI4_DATA8 */
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[ 1] = RCAR_GP_PIN(2, 8), /* VI4_DATA7 */
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[ 2] = RCAR_GP_PIN(2, 7), /* VI4_DATA6 */
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[ 3] = RCAR_GP_PIN(2, 6), /* VI4_DATA5 */
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[ 4] = RCAR_GP_PIN(2, 5), /* VI4_DATA4 */
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[ 5] = RCAR_GP_PIN(2, 4), /* VI4_DATA3 */
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[ 6] = RCAR_GP_PIN(2, 3), /* VI4_DATA2 */
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[ 7] = RCAR_GP_PIN(2, 2), /* VI4_DATA1 */
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[ 8] = RCAR_GP_PIN(2, 1), /* VI4_DATA0 */
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[ 9] = RCAR_GP_PIN(2, 0), /* VI4_CLK */
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[10] = RCAR_GP_PIN(1, 31), /* QPOLB */
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[11] = RCAR_GP_PIN(1, 30), /* QPOLA */
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[12] = RCAR_GP_PIN(1, 29), /* DU_CDE */
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[13] = RCAR_GP_PIN(1, 28), /* DU_DISP/CDE */
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[14] = RCAR_GP_PIN(1, 27), /* DU_DISP */
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[15] = RCAR_GP_PIN(1, 26), /* DU_VSYNC */
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[16] = RCAR_GP_PIN(1, 25), /* DU_HSYNC */
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[17] = RCAR_GP_PIN(1, 24), /* DU_DOTCLKOUT0 */
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[18] = RCAR_GP_PIN(1, 23), /* DU_DR7 */
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[19] = RCAR_GP_PIN(1, 22), /* DU_DR6 */
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[20] = RCAR_GP_PIN(1, 21), /* DU_DR5 */
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[21] = RCAR_GP_PIN(1, 20), /* DU_DR4 */
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[22] = RCAR_GP_PIN(1, 19), /* DU_DR3 */
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[23] = RCAR_GP_PIN(1, 18), /* DU_DR2 */
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[24] = RCAR_GP_PIN(1, 17), /* DU_DR1 */
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[25] = RCAR_GP_PIN(1, 16), /* DU_DR0 */
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[26] = RCAR_GP_PIN(1, 15), /* DU_DG7 */
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[27] = RCAR_GP_PIN(1, 14), /* DU_DG6 */
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[28] = RCAR_GP_PIN(1, 13), /* DU_DG5 */
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[29] = RCAR_GP_PIN(1, 12), /* DU_DG4 */
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[30] = RCAR_GP_PIN(1, 11), /* DU_DG3 */
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[31] = RCAR_GP_PIN(1, 10), /* DU_DG2 */
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} },
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{ PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
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[ 0] = RCAR_GP_PIN(3, 8), /* NFDATA6 */
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[ 1] = RCAR_GP_PIN(3, 7), /* NFDATA5 */
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[ 2] = RCAR_GP_PIN(3, 6), /* NFDATA4 */
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[ 3] = RCAR_GP_PIN(3, 5), /* NFDATA3 */
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[ 4] = RCAR_GP_PIN(3, 4), /* NFDATA2 */
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[ 5] = RCAR_GP_PIN(3, 3), /* NFDATA1 */
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[ 6] = RCAR_GP_PIN(3, 2), /* NFDATA0 */
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[ 7] = RCAR_GP_PIN(3, 1), /* NFWE# (PUEN) / NFRE# (PUD) */
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[ 8] = RCAR_GP_PIN(3, 0), /* NFRE# (PUEN) / NFWE# (PUD) */
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[ 9] = RCAR_GP_PIN(4, 0), /* NFRB# */
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[10] = RCAR_GP_PIN(2, 31), /* NFCE# */
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[11] = RCAR_GP_PIN(2, 30), /* NFCLE */
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[12] = RCAR_GP_PIN(2, 29), /* NFALE */
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[13] = RCAR_GP_PIN(2, 28), /* VI4_CLKENB */
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[14] = RCAR_GP_PIN(2, 27), /* VI4_FIELD */
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[15] = RCAR_GP_PIN(2, 26), /* VI4_HSYNC# */
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[16] = RCAR_GP_PIN(2, 25), /* VI4_VSYNC# */
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[17] = RCAR_GP_PIN(2, 24), /* VI4_DATA23 */
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[18] = RCAR_GP_PIN(2, 23), /* VI4_DATA22 */
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[19] = RCAR_GP_PIN(2, 22), /* VI4_DATA21 */
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[20] = RCAR_GP_PIN(2, 21), /* VI4_DATA20 */
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[21] = RCAR_GP_PIN(2, 20), /* VI4_DATA19 */
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[22] = RCAR_GP_PIN(2, 19), /* VI4_DATA18 */
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[23] = RCAR_GP_PIN(2, 18), /* VI4_DATA17 */
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[24] = RCAR_GP_PIN(2, 17), /* VI4_DATA16 */
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[25] = RCAR_GP_PIN(2, 16), /* VI4_DATA15 */
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[26] = RCAR_GP_PIN(2, 15), /* VI4_DATA14 */
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[27] = RCAR_GP_PIN(2, 14), /* VI4_DATA13 */
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[28] = RCAR_GP_PIN(2, 13), /* VI4_DATA12 */
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[29] = RCAR_GP_PIN(2, 12), /* VI4_DATA11 */
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[30] = RCAR_GP_PIN(2, 11), /* VI4_DATA10 */
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[31] = RCAR_GP_PIN(2, 10), /* VI4_DATA9 */
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} },
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{ PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
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[ 0] = RCAR_GP_PIN(4, 31), /* CAN0_RX_A */
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[ 1] = RCAR_GP_PIN(5, 2), /* CAN_CLK */
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[ 2] = RCAR_GP_PIN(5, 1), /* TPU0TO1_A */
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[ 3] = RCAR_GP_PIN(5, 0), /* TPU0TO0_A */
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[ 4] = RCAR_GP_PIN(4, 27), /* TX2 */
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[ 5] = RCAR_GP_PIN(4, 26), /* RX2 */
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[ 6] = RCAR_GP_PIN(4, 25), /* SCK2 */
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[ 7] = RCAR_GP_PIN(4, 24), /* TX1_A */
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[ 8] = RCAR_GP_PIN(4, 23), /* RX1_A */
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[ 9] = RCAR_GP_PIN(4, 22), /* SCK1_A */
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[10] = RCAR_GP_PIN(4, 21), /* TX0_A */
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[11] = RCAR_GP_PIN(4, 20), /* RX0_A */
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[12] = RCAR_GP_PIN(4, 19), /* SCK0_A */
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[13] = RCAR_GP_PIN(4, 18), /* MSIOF1_RXD */
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[14] = RCAR_GP_PIN(4, 17), /* MSIOF1_TXD */
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[15] = RCAR_GP_PIN(4, 16), /* MSIOF1_SCK */
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[16] = RCAR_GP_PIN(4, 15), /* MSIOF0_RXD */
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[17] = RCAR_GP_PIN(4, 14), /* MSIOF0_TXD */
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[18] = RCAR_GP_PIN(4, 13), /* MSIOF0_SYNC */
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[19] = RCAR_GP_PIN(4, 12), /* MSIOF0_SCK */
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[20] = RCAR_GP_PIN(4, 11), /* SDA1 */
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[21] = RCAR_GP_PIN(4, 10), /* SCL1 */
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[22] = RCAR_GP_PIN(4, 9), /* SDA0 */
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[23] = RCAR_GP_PIN(4, 8), /* SCL0 */
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[24] = RCAR_GP_PIN(4, 7), /* SSI_WS4_A */
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[25] = RCAR_GP_PIN(4, 6), /* SSI_SDATA4_A */
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[26] = RCAR_GP_PIN(4, 5), /* SSI_SCK4_A */
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[27] = RCAR_GP_PIN(4, 4), /* SSI_WS34 */
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[28] = RCAR_GP_PIN(4, 3), /* SSI_SDATA3 */
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[29] = RCAR_GP_PIN(4, 2), /* SSI_SCK34 */
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[30] = RCAR_GP_PIN(4, 1), /* AUDIO_CLKA */
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[31] = RCAR_GP_PIN(3, 9), /* NFDATA7 */
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} },
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{ PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
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[ 0] = RCAR_GP_PIN(6, 10), /* QSPI1_IO3 */
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[ 1] = RCAR_GP_PIN(6, 9), /* QSPI1_IO2 */
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[ 2] = RCAR_GP_PIN(6, 8), /* QSPI1_MISO_IO1 */
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[ 3] = RCAR_GP_PIN(6, 7), /* QSPI1_MOSI_IO0 */
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[ 4] = RCAR_GP_PIN(6, 6), /* QSPI1_SPCLK */
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[ 5] = RCAR_GP_PIN(6, 5), /* QSPI0_SSL */
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[ 6] = RCAR_GP_PIN(6, 4), /* QSPI0_IO3 */
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[ 7] = RCAR_GP_PIN(6, 3), /* QSPI0_IO2 */
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[ 8] = RCAR_GP_PIN(6, 2), /* QSPI0_MISO_IO1 */
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[ 9] = RCAR_GP_PIN(6, 1), /* QSPI0_MOSI_IO0 */
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[10] = RCAR_GP_PIN(6, 0), /* QSPI0_SPCLK */
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[11] = RCAR_GP_PIN(5, 20), /* AVB0_LINK */
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[12] = RCAR_GP_PIN(5, 19), /* AVB0_PHY_INT */
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[13] = RCAR_GP_PIN(5, 18), /* AVB0_MAGIC */
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[14] = RCAR_GP_PIN(5, 17), /* AVB0_MDC */
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[15] = RCAR_GP_PIN(5, 16), /* AVB0_MDIO */
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[16] = RCAR_GP_PIN(5, 15), /* AVB0_TXCREFCLK */
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[17] = RCAR_GP_PIN(5, 14), /* AVB0_TD3 */
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[18] = RCAR_GP_PIN(5, 13), /* AVB0_TD2 */
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[19] = RCAR_GP_PIN(5, 12), /* AVB0_TD1 */
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[20] = RCAR_GP_PIN(5, 11), /* AVB0_TD0 */
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[21] = RCAR_GP_PIN(5, 10), /* AVB0_TXC */
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[22] = RCAR_GP_PIN(5, 9), /* AVB0_TX_CTL */
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[23] = RCAR_GP_PIN(5, 8), /* AVB0_RD3 */
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[24] = RCAR_GP_PIN(5, 7), /* AVB0_RD2 */
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[25] = RCAR_GP_PIN(5, 6), /* AVB0_RD1 */
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[26] = RCAR_GP_PIN(5, 5), /* AVB0_RD0 */
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[27] = RCAR_GP_PIN(5, 4), /* AVB0_RXC */
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[28] = RCAR_GP_PIN(5, 3), /* AVB0_RX_CTL */
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[29] = RCAR_GP_PIN(4, 30), /* CAN1_TX_A */
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[30] = RCAR_GP_PIN(4, 29), /* CAN1_RX_A */
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[31] = RCAR_GP_PIN(4, 28), /* CAN0_TX_A */
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} },
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{ PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD4", 0xe6060454) {
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[ 0] = SH_PFC_PIN_NONE,
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[ 1] = SH_PFC_PIN_NONE,
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[ 2] = SH_PFC_PIN_NONE,
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[ 3] = SH_PFC_PIN_NONE,
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[ 4] = SH_PFC_PIN_NONE,
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[ 5] = SH_PFC_PIN_NONE,
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[ 6] = SH_PFC_PIN_NONE,
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[ 7] = SH_PFC_PIN_NONE,
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[ 8] = SH_PFC_PIN_NONE,
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[ 9] = SH_PFC_PIN_NONE,
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[10] = SH_PFC_PIN_NONE,
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[11] = SH_PFC_PIN_NONE,
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[12] = SH_PFC_PIN_NONE,
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[13] = SH_PFC_PIN_NONE,
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[14] = SH_PFC_PIN_NONE,
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[15] = SH_PFC_PIN_NONE,
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[16] = SH_PFC_PIN_NONE,
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[17] = SH_PFC_PIN_NONE,
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[18] = SH_PFC_PIN_NONE,
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[19] = SH_PFC_PIN_NONE,
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[20] = SH_PFC_PIN_NONE,
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[21] = SH_PFC_PIN_NONE,
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[22] = SH_PFC_PIN_NONE,
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[23] = SH_PFC_PIN_NONE,
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[24] = SH_PFC_PIN_NONE,
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[25] = SH_PFC_PIN_NONE,
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[26] = SH_PFC_PIN_NONE,
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[27] = SH_PFC_PIN_NONE,
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[28] = SH_PFC_PIN_NONE,
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[29] = RCAR_GP_PIN(6, 13), /* RPC_INT# */
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[30] = RCAR_GP_PIN(6, 12), /* RPC_RESET# */
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[31] = RCAR_GP_PIN(6, 11), /* QSPI1_SSL */
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} },
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{ /* sentinel */ }
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};
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enum ioctrl_regs {
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TDSELCTRL,
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};
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@ -2843,8 +3071,83 @@ static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
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{ /* sentinel */ },
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};
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static const struct pinmux_bias_reg *
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r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
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unsigned int *puen_bit, unsigned int *pud_bit)
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{
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const struct pinmux_bias_reg *reg;
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unsigned int bit;
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reg = rcar_pin_to_bias_reg(pfc, pin, &bit);
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if (!reg)
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return reg;
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*puen_bit = bit;
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/* NFWE# and NFRE# use different bit positions in PUD2 */
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switch (pin) {
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||||
case RCAR_GP_PIN(3, 0): /* NFRE# */
|
||||
*pud_bit = 7;
|
||||
break;
|
||||
|
||||
case RCAR_GP_PIN(3, 1): /* NFWE# */
|
||||
*pud_bit = 8;
|
||||
break;
|
||||
|
||||
default:
|
||||
*pud_bit = bit;
|
||||
break;
|
||||
}
|
||||
|
||||
return reg;
|
||||
}
|
||||
|
||||
static unsigned int r8a77995_pinmux_get_bias(struct sh_pfc *pfc,
|
||||
unsigned int pin)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int puen_bit, pud_bit;
|
||||
|
||||
reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit);
|
||||
if (!reg)
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
|
||||
if (!(sh_pfc_read(pfc, reg->puen) & BIT(puen_bit)))
|
||||
return PIN_CONFIG_BIAS_DISABLE;
|
||||
else if (sh_pfc_read(pfc, reg->pud) & BIT(pud_bit))
|
||||
return PIN_CONFIG_BIAS_PULL_UP;
|
||||
else
|
||||
return PIN_CONFIG_BIAS_PULL_DOWN;
|
||||
}
|
||||
|
||||
static void r8a77995_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias)
|
||||
{
|
||||
const struct pinmux_bias_reg *reg;
|
||||
unsigned int puen_bit, pud_bit;
|
||||
u32 enable, updown;
|
||||
|
||||
reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit);
|
||||
if (!reg)
|
||||
return;
|
||||
|
||||
enable = sh_pfc_read(pfc, reg->puen) & ~BIT(puen_bit);
|
||||
if (bias != PIN_CONFIG_BIAS_DISABLE) {
|
||||
enable |= BIT(puen_bit);
|
||||
|
||||
updown = sh_pfc_read(pfc, reg->pud) & ~BIT(pud_bit);
|
||||
if (bias == PIN_CONFIG_BIAS_PULL_UP)
|
||||
updown |= BIT(pud_bit);
|
||||
|
||||
sh_pfc_write(pfc, reg->pud, updown);
|
||||
}
|
||||
sh_pfc_write(pfc, reg->puen, enable);
|
||||
}
|
||||
|
||||
static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
|
||||
.pin_to_pocctrl = r8a77995_pin_to_pocctrl,
|
||||
.get_bias = r8a77995_pinmux_get_bias,
|
||||
.set_bias = r8a77995_pinmux_set_bias,
|
||||
};
|
||||
|
||||
const struct sh_pfc_soc_info r8a77995_pinmux_info = {
|
||||
|
|
@ -2862,6 +3165,7 @@ const struct sh_pfc_soc_info r8a77995_pinmux_info = {
|
|||
.nr_functions = ARRAY_SIZE(pinmux_functions),
|
||||
|
||||
.cfg_regs = pinmux_config_regs,
|
||||
.bias_regs = pinmux_bias_regs,
|
||||
.ioctrl_regs = pinmux_ioctrl_regs,
|
||||
|
||||
.pinmux_data = pinmux_data,
|
||||
|
|
|
|||
|
|
@ -841,7 +841,7 @@ int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
|
|||
return pinctrl_enable(pmx->pctl);
|
||||
}
|
||||
|
||||
static const struct pinmux_bias_reg *
|
||||
const struct pinmux_bias_reg *
|
||||
rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int *bit)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -781,6 +781,9 @@ extern const struct sh_pfc_soc_info shx3_pinmux_info;
|
|||
/*
|
||||
* Bias helpers
|
||||
*/
|
||||
const struct pinmux_bias_reg *
|
||||
rcar_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int *bit);
|
||||
unsigned int rcar_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin);
|
||||
void rcar_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
|
||||
unsigned int bias);
|
||||
|
|
|
|||
Loading…
Reference in a new issue