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ARM: dts: Add DISP1 power domain for exynos5420
The DISP1 power domain on Exynos5420 SoC includes the FIMD1, MIXER and HDMI modules. Add a device node for this power domain and mark these modules as consumer of the DISP1 power domain. When a power domain is powered on and off, the input clocks of the devices attached to it are reparented. So a reference to the input and parent clocks of the devices are needed to manage that. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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1 changed files with 17 additions and 0 deletions
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@ -274,6 +274,20 @@ msc_pd: power-domain@10044120 {
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#power-domain-cells = <0>;
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};
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disp_pd: power-domain@100440C0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x100440C0 0x20>;
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#power-domain-cells = <0>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>,
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<&clock CLK_MOUT_USER_ACLK200_DISP1>,
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<&clock CLK_MOUT_SW_ACLK300>,
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<&clock CLK_MOUT_USER_ACLK300_DISP1>,
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<&clock CLK_MOUT_SW_ACLK400>,
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<&clock CLK_MOUT_USER_ACLK400_DISP1>;
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clock-names = "oscclk", "pclk0", "clk0",
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"pclk1", "clk1", "pclk2", "clk2";
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};
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pinctrl_0: pinctrl@13400000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x13400000 0x1000>;
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@ -541,6 +555,7 @@ dsi@14500000 {
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fimd: fimd@14400000 {
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clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
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clock-names = "sclk_fimd", "fimd";
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power-domains = <&disp_pd>;
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};
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adc: adc@12D10000 {
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@ -714,6 +729,7 @@ hdmi: hdmi@14530000 {
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phy = <&hdmiphy>;
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samsung,syscon-phandle = <&pmu_system_controller>;
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status = "disabled";
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power-domains = <&disp_pd>;
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};
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hdmiphy: hdmiphy@145D0000 {
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@ -726,6 +742,7 @@ mixer: mixer@14450000 {
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interrupts = <0 94 0>;
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clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
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clock-names = "mixer", "sclk_hdmi";
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power-domains = <&disp_pd>;
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};
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gsc_0: video-scaler@13e00000 {
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