drm/amd/display: Enforce 60us prefetch for 200Mhz DCFCLK modes
commit b504f99cca
upstream.
[Description]
- Due to bandwidth / arbitration issues at 200Mhz DCFCLK,
we want to enforce minimum 60us of prefetch to avoid
intermittent underflow issues
- Since 60us prefetch is already enforced for UCLK DPM0,
and many DCFCLK's > 200Mhz are mapped to UCLK DPM1, in
theory there should not be any UCLK DPM regressions by
enforcing greater prefetch
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -807,7 +807,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
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v->SwathHeightY[k],
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v->SwathHeightC[k],
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TWait,
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v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ?
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(v->DRAMSpeedPerState[mode_lib->vba.VoltageLevel] <= MEM_STROBE_FREQ_MHZ ||
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v->DCFCLKPerState[mode_lib->vba.VoltageLevel] <= MIN_DCFCLK_FREQ_MHZ) ?
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mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
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/* Output */
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&v->DSTXAfterScaler[k],
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@ -3289,7 +3290,7 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
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v->swath_width_chroma_ub_this_state[k],
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v->SwathHeightYThisState[k],
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v->SwathHeightCThisState[k], v->TWait,
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v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ ?
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(v->DRAMSpeedPerState[i] <= MEM_STROBE_FREQ_MHZ || v->DCFCLKState[i][j] <= MIN_DCFCLK_FREQ_MHZ) ?
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mode_lib->vba.ip.min_prefetch_in_strobe_us : 0,
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/* Output */
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@ -52,6 +52,7 @@
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#define BPP_BLENDED_PIPE 0xffffffff
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#define MEM_STROBE_FREQ_MHZ 1600
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#define MIN_DCFCLK_FREQ_MHZ 200
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#define MEM_STROBE_MAX_DELIVERY_TIME_US 60.0
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struct display_mode_lib;
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