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powerpc/mm: Cleanup handling of execute permission
This is an attempt at cleaning up a bit the way we handle execute permission on powerpc. _PAGE_HWEXEC is gone, _PAGE_EXEC is now only defined by CPUs that can do something with it, and the myriad of #ifdef's in the I$/D$ coherency code is reduced to 2 cases that hopefully should cover everything. The logic on BookE is a little bit different than what it was though not by much. Since now, _PAGE_EXEC will be set by the generic code for executable pages, we need to filter out if they are unclean and recover it. However, I don't expect the code to be more bloated than it already was in that area due to that change. I could boast that this brings proper enforcing of per-page execute permissions to all BookE and 40x but in fact, we've had that now for some time as a side effect of my previous rework in that area (and I didn't even know it :-) We would only enable execute permission if the page was cache clean and we would only cache clean it if we took and exec fault. Since we now enforce that the later only work if VM_EXEC is part of the VMA flags, we de-fact already enforce per-page execute permissions... Unless I missed something Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
parent
f480fe3916
commit
ea3cc330ac
15 changed files with 149 additions and 87 deletions
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@ -186,7 +186,7 @@ static inline unsigned long pte_update(pte_t *p,
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#endif /* !PTE_ATOMIC_UPDATES */
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#ifdef CONFIG_44x
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if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
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if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
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icache_44x_need_flush = 1;
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#endif
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return old;
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@ -217,7 +217,7 @@ static inline unsigned long long pte_update(pte_t *p,
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#endif /* !PTE_ATOMIC_UPDATES */
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#ifdef CONFIG_44x
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if ((old & _PAGE_USER) && (old & _PAGE_HWEXEC))
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if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
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icache_44x_need_flush = 1;
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#endif
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return old;
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@ -267,8 +267,7 @@ static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
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static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
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{
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unsigned long bits = pte_val(entry) &
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(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW |
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_PAGE_HWEXEC | _PAGE_EXEC);
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(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
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pte_update(ptep, 0, bits);
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}
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@ -313,8 +313,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
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static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
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{
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unsigned long bits = pte_val(entry) &
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(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW |
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_PAGE_EXEC | _PAGE_HWEXEC);
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(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
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#ifdef PTE_ATOMIC_UPDATES
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unsigned long old, tmp;
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@ -46,7 +46,7 @@
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#define _PAGE_RW 0x040 /* software: Writes permitted */
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#define _PAGE_DIRTY 0x080 /* software: dirty page */
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#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
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#define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
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#define _PAGE_EXEC 0x200 /* hardware: EX permission */
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#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
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#define _PMD_PRESENT 0x400 /* PMD points to page of PTEs */
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@ -78,7 +78,7 @@
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#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */
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#define _PAGE_RW 0x00000002 /* S: Write permission */
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#define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */
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#define _PAGE_HWEXEC 0x00000004 /* H: Execute permission */
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#define _PAGE_EXEC 0x00000004 /* H: Execute permission */
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#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */
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#define _PAGE_DIRTY 0x00000010 /* S: Page dirty */
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#define _PAGE_SPECIAL 0x00000020 /* S: Special page */
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@ -36,7 +36,6 @@
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/* These five software bits must be masked out when the entry is loaded
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* into the TLB.
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*/
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#define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */
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#define _PAGE_GUARDED 0x0010 /* software: guarded access */
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#define _PAGE_DIRTY 0x0020 /* software: page changed */
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#define _PAGE_RW 0x0040 /* software: user write access allowed */
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@ -37,12 +37,13 @@
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#define _PAGE_WRITETHRU 0x800000 /* W: cache write-through */
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/* "Higher level" linux bit combinations */
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#define _PAGE_EXEC _PAGE_BAP_SX /* Can be executed from potentially */
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#define _PAGE_HWEXEC _PAGE_BAP_UX /* .. and was cache cleaned */
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#define _PAGE_RW (_PAGE_BAP_SW | _PAGE_BAP_UW) /* User write permission */
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#define _PAGE_KERNEL_RW (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY)
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#define _PAGE_KERNEL_RO (_PAGE_BAP_SR)
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#define _PAGE_USER (_PAGE_BAP_UR | _PAGE_BAP_SR) /* Can be read */
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#define _PAGE_EXEC _PAGE_BAP_UX /* .. and was cache cleaned */
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#define _PAGE_RW (_PAGE_BAP_SW | _PAGE_BAP_UW) /* User write permission */
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#define _PAGE_KERNEL_RW (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY)
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#define _PAGE_KERNEL_RO (_PAGE_BAP_SR)
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#define _PAGE_KERNEL_RWX (_PAGE_BAP_SW | _PAGE_BAP_SR | _PAGE_DIRTY | _PAGE_BAP_SX)
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#define _PAGE_KERNEL_ROX (_PAGE_BAP_SR | _PAGE_BAP_SX)
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#define _PAGE_USER (_PAGE_BAP_UR | _PAGE_BAP_SR) /* Can be read */
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#define _PAGE_HASHPTE 0
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#define _PAGE_BUSY 0
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@ -13,9 +13,6 @@
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#ifndef _PAGE_HWWRITE
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#define _PAGE_HWWRITE 0
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#endif
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#ifndef _PAGE_HWEXEC
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#define _PAGE_HWEXEC 0
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#endif
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#ifndef _PAGE_EXEC
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#define _PAGE_EXEC 0
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#endif
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@ -48,10 +45,16 @@
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#define PMD_PAGE_SIZE(pmd) bad_call_to_PMD_PAGE_SIZE()
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#endif
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#ifndef _PAGE_KERNEL_RO
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#define _PAGE_KERNEL_RO 0
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#define _PAGE_KERNEL_RO 0
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#endif
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#ifndef _PAGE_KERNEL_ROX
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#define _PAGE_KERNEL_ROX (_PAGE_EXEC)
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#endif
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#ifndef _PAGE_KERNEL_RW
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#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)
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#define _PAGE_KERNEL_RW (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE)
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#endif
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#ifndef _PAGE_KERNEL_RWX
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#define _PAGE_KERNEL_RWX (_PAGE_DIRTY | _PAGE_RW | _PAGE_HWWRITE | _PAGE_EXEC)
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#endif
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#ifndef _PAGE_HPTEFLAGS
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#define _PAGE_HPTEFLAGS _PAGE_HASHPTE
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@ -96,8 +99,7 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
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#define PAGE_PROT_BITS (_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \
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_PAGE_WRITETHRU | _PAGE_ENDIAN | _PAGE_4K_PFN | \
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_PAGE_USER | _PAGE_ACCESSED | \
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_PAGE_RW | _PAGE_HWWRITE | _PAGE_DIRTY | \
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_PAGE_EXEC | _PAGE_HWEXEC)
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_PAGE_RW | _PAGE_HWWRITE | _PAGE_DIRTY | _PAGE_EXEC)
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/*
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* We define 2 sets of base prot bits, one for basic pages (ie,
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@ -154,11 +156,9 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
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_PAGE_NO_CACHE)
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#define PAGE_KERNEL_NCG __pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \
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_PAGE_NO_CACHE | _PAGE_GUARDED)
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#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RW | _PAGE_EXEC | \
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_PAGE_HWEXEC)
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#define PAGE_KERNEL_X __pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)
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#define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)
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#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_RO | _PAGE_EXEC | \
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_PAGE_HWEXEC)
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#define PAGE_KERNEL_ROX __pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
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/* Protection used for kernel text. We want the debuggers to be able to
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* set breakpoints anywhere, so don't write protect the kernel text
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@ -23,7 +23,7 @@
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#define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */
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#define _PAGE_RW 0x00004 /* S: Write permission (SW) */
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#define _PAGE_DIRTY 0x00008 /* S: Page dirty */
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#define _PAGE_HWEXEC 0x00010 /* H: SX permission */
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#define _PAGE_EXEC 0x00010 /* H: SX permission */
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#define _PAGE_ACCESSED 0x00020 /* S: Page referenced */
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#define _PAGE_ENDIAN 0x00040 /* H: E bit */
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@ -26,7 +26,6 @@
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#define _PAGE_WRITETHRU 0x040 /* W: cache write-through */
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#define _PAGE_DIRTY 0x080 /* C: page changed */
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#define _PAGE_ACCESSED 0x100 /* R: page referenced */
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#define _PAGE_EXEC 0x200 /* software: i-cache coherency required */
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#define _PAGE_RW 0x400 /* software: user write access allowed */
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#define _PAGE_SPECIAL 0x800 /* software: Special page */
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@ -497,7 +497,7 @@ tlb_44x_patch_hwater_D:
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mtspr SPRN_MMUCR,r12
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/* Make up the required permissions */
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li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC
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li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
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/* Compute pgdir/pmd offset */
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rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
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@ -643,7 +643,7 @@ interrupt_base:
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4:
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/* Make up the required permissions */
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li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_HWEXEC
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li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
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FIND_PTE
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andc. r13,r13,r11 /* Check permission */
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#endif
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mtspr SPRN_MAS2, r12
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li r10, (_PAGE_HWEXEC | _PAGE_PRESENT)
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li r10, (_PAGE_EXEC | _PAGE_PRESENT)
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rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
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and r12, r11, r10
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andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
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@ -105,7 +105,7 @@ unsigned long __init mmu_mapin_ram(void)
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while (s >= LARGE_PAGE_SIZE_16M) {
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pmd_t *pmdp;
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unsigned long val = p | _PMD_SIZE_16M | _PAGE_HWEXEC | _PAGE_HWWRITE;
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unsigned long val = p | _PMD_SIZE_16M | _PAGE_EXEC | _PAGE_HWWRITE;
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pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v);
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pmd_val(*pmdp++) = val;
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while (s >= LARGE_PAGE_SIZE_4M) {
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pmd_t *pmdp;
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unsigned long val = p | _PMD_SIZE_4M | _PAGE_HWEXEC | _PAGE_HWWRITE;
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unsigned long val = p | _PMD_SIZE_4M | _PAGE_EXEC | _PAGE_HWWRITE;
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pmdp = pmd_offset(pud_offset(pgd_offset_k(v), v), v);
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pmd_val(*pmdp) = val;
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@ -128,28 +128,6 @@ void pte_free_finish(void)
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#endif /* CONFIG_SMP */
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/*
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* Handle i/d cache flushing, called from set_pte_at() or ptep_set_access_flags()
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*/
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static pte_t do_dcache_icache_coherency(pte_t pte)
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{
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unsigned long pfn = pte_pfn(pte);
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struct page *page;
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if (unlikely(!pfn_valid(pfn)))
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return pte;
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page = pfn_to_page(pfn);
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if (!PageReserved(page) && !test_bit(PG_arch_1, &page->flags)) {
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pr_devel("do_dcache_icache_coherency... flushing\n");
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flush_dcache_icache_page(page);
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set_bit(PG_arch_1, &page->flags);
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}
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else
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pr_devel("do_dcache_icache_coherency... already clean\n");
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return __pte(pte_val(pte) | _PAGE_HWEXEC);
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}
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static inline int is_exec_fault(void)
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{
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return current->thread.regs && TRAP(current->thread.regs) == 0x400;
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@ -157,49 +135,139 @@ static inline int is_exec_fault(void)
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/* We only try to do i/d cache coherency on stuff that looks like
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* reasonably "normal" PTEs. We currently require a PTE to be present
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* and we avoid _PAGE_SPECIAL and _PAGE_NO_CACHE
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* and we avoid _PAGE_SPECIAL and _PAGE_NO_CACHE. We also only do that
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* on userspace PTEs
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*/
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static inline int pte_looks_normal(pte_t pte)
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{
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return (pte_val(pte) &
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(_PAGE_PRESENT | _PAGE_SPECIAL | _PAGE_NO_CACHE)) ==
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(_PAGE_PRESENT);
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(_PAGE_PRESENT | _PAGE_SPECIAL | _PAGE_NO_CACHE | _PAGE_USER)) ==
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(_PAGE_PRESENT | _PAGE_USER);
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}
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#if defined(CONFIG_PPC_STD_MMU)
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struct page * maybe_pte_to_page(pte_t pte)
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{
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unsigned long pfn = pte_pfn(pte);
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struct page *page;
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if (unlikely(!pfn_valid(pfn)))
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return NULL;
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page = pfn_to_page(pfn);
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if (PageReserved(page))
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return NULL;
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return page;
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}
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#if defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0
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/* Server-style MMU handles coherency when hashing if HW exec permission
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* is supposed per page (currently 64-bit only). Else, we always flush
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* valid PTEs in set_pte.
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* is supposed per page (currently 64-bit only). If not, then, we always
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* flush the cache for valid PTEs in set_pte. Embedded CPU without HW exec
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* support falls into the same category.
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*/
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static inline int pte_need_exec_flush(pte_t pte, int set_pte)
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static pte_t set_pte_filter(pte_t pte)
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{
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return set_pte && pte_looks_normal(pte) &&
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!(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
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cpu_has_feature(CPU_FTR_NOEXECUTE));
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pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
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if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
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cpu_has_feature(CPU_FTR_NOEXECUTE))) {
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struct page *pg = maybe_pte_to_page(pte);
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if (!pg)
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return pte;
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if (!test_bit(PG_arch_1, &pg->flags)) {
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flush_dcache_icache_page(pg);
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set_bit(PG_arch_1, &pg->flags);
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}
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}
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return pte;
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}
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#elif _PAGE_HWEXEC == 0
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/* Embedded type MMU without HW exec support (8xx only so far), we flush
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* the cache for any present PTE
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static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
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int dirty)
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{
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return pte;
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}
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#else /* defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0 */
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/* Embedded type MMU with HW exec support. This is a bit more complicated
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* as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so
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* instead we "filter out" the exec permission for non clean pages.
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*/
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static inline int pte_need_exec_flush(pte_t pte, int set_pte)
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static pte_t set_pte_filter(pte_t pte)
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{
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return set_pte && pte_looks_normal(pte);
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struct page *pg;
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/* No exec permission in the first place, move on */
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if (!(pte_val(pte) & _PAGE_EXEC) || !pte_looks_normal(pte))
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return pte;
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/* If you set _PAGE_EXEC on weird pages you're on your own */
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pg = maybe_pte_to_page(pte);
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if (unlikely(!pg))
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return pte;
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/* If the page clean, we move on */
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if (test_bit(PG_arch_1, &pg->flags))
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return pte;
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/* If it's an exec fault, we flush the cache and make it clean */
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if (is_exec_fault()) {
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flush_dcache_icache_page(pg);
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set_bit(PG_arch_1, &pg->flags);
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return pte;
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}
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/* Else, we filter out _PAGE_EXEC */
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return __pte(pte_val(pte) & ~_PAGE_EXEC);
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}
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#else
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/* Other embedded CPUs with HW exec support per-page, we flush on exec
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* fault if HWEXEC is not set
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*/
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static inline int pte_need_exec_flush(pte_t pte, int set_pte)
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static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
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int dirty)
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{
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return pte_looks_normal(pte) && is_exec_fault() &&
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!(pte_val(pte) & _PAGE_HWEXEC);
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struct page *pg;
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/* So here, we only care about exec faults, as we use them
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* to recover lost _PAGE_EXEC and perform I$/D$ coherency
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* if necessary. Also if _PAGE_EXEC is already set, same deal,
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* we just bail out
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*/
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if (dirty || (pte_val(pte) & _PAGE_EXEC) || !is_exec_fault())
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return pte;
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#ifdef CONFIG_DEBUG_VM
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/* So this is an exec fault, _PAGE_EXEC is not set. If it was
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* an error we would have bailed out earlier in do_page_fault()
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* but let's make sure of it
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*/
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if (WARN_ON(!(vma->vm_flags & VM_EXEC)))
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return pte;
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#endif /* CONFIG_DEBUG_VM */
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/* If you set _PAGE_EXEC on weird pages you're on your own */
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pg = maybe_pte_to_page(pte);
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if (unlikely(!pg))
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goto bail;
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|
||||
/* If the page is already clean, we move on */
|
||||
if (test_bit(PG_arch_1, &pg->flags))
|
||||
goto bail;
|
||||
|
||||
/* Clean the page and set PG_arch_1 */
|
||||
flush_dcache_icache_page(pg);
|
||||
set_bit(PG_arch_1, &pg->flags);
|
||||
|
||||
bail:
|
||||
return __pte(pte_val(pte) | _PAGE_EXEC);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* !(defined(CONFIG_PPC_STD_MMU) || _PAGE_EXEC == 0) */
|
||||
|
||||
/*
|
||||
* set_pte stores a linux PTE into the linux page table.
|
||||
*/
|
||||
void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
|
||||
void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
|
||||
pte_t pte)
|
||||
{
|
||||
#ifdef CONFIG_DEBUG_VM
|
||||
WARN_ON(pte_present(*ptep));
|
||||
|
@ -208,9 +276,7 @@ void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte
|
|||
* this context might not have been activated yet when this
|
||||
* is called.
|
||||
*/
|
||||
pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
|
||||
if (pte_need_exec_flush(pte, 1))
|
||||
pte = do_dcache_icache_coherency(pte);
|
||||
pte = set_pte_filter(pte);
|
||||
|
||||
/* Perform the setting of the PTE */
|
||||
__set_pte_at(mm, addr, ptep, pte, 0);
|
||||
|
@ -227,8 +293,7 @@ int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
|
|||
pte_t *ptep, pte_t entry, int dirty)
|
||||
{
|
||||
int changed;
|
||||
if (!dirty && pte_need_exec_flush(entry, 0))
|
||||
entry = do_dcache_icache_coherency(entry);
|
||||
entry = set_access_flags_filter(entry, vma, dirty);
|
||||
changed = !pte_same(*(ptep), entry);
|
||||
if (changed) {
|
||||
if (!(vma->vm_flags & VM_HUGETLB))
|
||||
|
|
|
@ -142,7 +142,7 @@ ioremap_flags(phys_addr_t addr, unsigned long size, unsigned long flags)
|
|||
flags |= _PAGE_DIRTY | _PAGE_HWWRITE;
|
||||
|
||||
/* we don't want to let _PAGE_USER and _PAGE_EXEC leak out */
|
||||
flags &= ~(_PAGE_USER | _PAGE_EXEC | _PAGE_HWEXEC);
|
||||
flags &= ~(_PAGE_USER | _PAGE_EXEC);
|
||||
|
||||
return __ioremap_caller(addr, size, flags, __builtin_return_address(0));
|
||||
}
|
||||
|
|
|
@ -133,7 +133,7 @@
|
|||
|
||||
/* We do the user/kernel test for the PID here along with the RW test
|
||||
*/
|
||||
li r11,_PAGE_PRESENT|_PAGE_HWEXEC /* Base perm */
|
||||
li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
|
||||
oris r11,r11,_PAGE_ACCESSED@h
|
||||
|
||||
cmpldi cr0,r15,0 /* Check for user region */
|
||||
|
@ -256,7 +256,7 @@ normal_tlb_miss_done:
|
|||
|
||||
normal_tlb_miss_access_fault:
|
||||
/* We need to check if it was an instruction miss */
|
||||
andi. r10,r11,_PAGE_HWEXEC
|
||||
andi. r10,r11,_PAGE_EXEC
|
||||
bne 1f
|
||||
ld r14,EX_TLB_DEAR(r12)
|
||||
ld r15,EX_TLB_ESR(r12)
|
||||
|
|
Loading…
Reference in a new issue