[PATCH] mbxfb: Add YUV video overlay support
This patch adds a way to create and use the video plane (YUV overlay) and
scaling video scaling features of the chip.
The overlay is configured, resized and modified using a device specific
ioctl.
Also included in this patch:
- If no platform data was passed, print an error and exit instead of crashing.
- Added a write_reg(_dly) macro. This improves readability when
manipulating chip registers. (no more udelay() after each write).
- Comments about some issues.
Signed-off-by: Raphael Assenat <raph@8d.com>
Cc: "Antonino A. Daplas" <adaplas@pol.net>
Acked-by: James Simmons <jsimmons@infradead.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Raphael Assenat
Linus Torvalds
parent
128806c3b3
commit
ea465250d4
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@ -1,8 +1,14 @@
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/*
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* linux/drivers/video/mbx/mbxfb.c
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*
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* Copyright (C) 2006 8D Technologies inc
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* Raphael Assenat <raph@8d.com>
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* - Added video overlay support
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* - Various improvements
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*
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* Copyright (C) 2006 Compulab, Ltd.
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* Mike Rapoport <mike@compulab.co.il>
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* - Creation of driver
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*
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* Based on pxafb.c
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*
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@ -19,6 +25,7 @@
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/uaccess.h>
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#include <asm/io.h>
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@ -29,6 +36,14 @@
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static unsigned long virt_base_2700;
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#define write_reg(val, reg) do { writel((val), (reg)); } while(0)
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/* Without this delay, the graphics appears somehow scaled and
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* there is a lot of jitter in scanlines. This delay is probably
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* needed only after setting some specific register(s) somewhere,
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* not all over the place... */
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#define write_reg_dly(val, reg) do { writel((val), reg); udelay(1000); } while(0)
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#define MIN_XRES 16
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#define MIN_YRES 16
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#define MAX_XRES 2048
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@ -257,19 +272,17 @@ static int mbxfb_set_par(struct fb_info *info)
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gsctrl &= ~(FMsk(GSCTRL_GSWIDTH) | FMsk(GSCTRL_GSHEIGHT));
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gsctrl |= Gsctrl_Width(info->var.xres) |
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Gsctrl_Height(info->var.yres);
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writel(gsctrl, GSCTRL);
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udelay(1000);
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write_reg_dly(gsctrl, GSCTRL);
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gsadr &= ~(FMsk(GSADR_SRCSTRIDE));
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gsadr |= Gsadr_Srcstride(info->var.xres * info->var.bits_per_pixel /
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(8 * 16) - 1);
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writel(gsadr, GSADR);
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udelay(1000);
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write_reg_dly(gsadr, GSADR);
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/* setup timings */
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var->pixclock = mbxfb_get_pixclock(info->var.pixclock, &div);
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writel((Disp_Pll_M(div.m) | Disp_Pll_N(div.n) |
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write_reg_dly((Disp_Pll_M(div.m) | Disp_Pll_N(div.n) |
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Disp_Pll_P(div.p) | DISP_PLL_EN), DISPPLL);
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hbps = var->hsync_len;
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@ -282,18 +295,20 @@ static int mbxfb_set_par(struct fb_info *info)
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vfps = vas + var->yres;
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vt = vfps + var->lower_margin;
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writel((Dht01_Hbps(hbps) | Dht01_Ht(ht)), DHT01);
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writel((Dht02_Hlbs(has) | Dht02_Has(has)), DHT02);
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writel((Dht03_Hfps(hfps) | Dht03_Hrbs(hfps)), DHT03);
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writel((Dhdet_Hdes(has) | Dhdet_Hdef(hfps)), DHDET);
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write_reg_dly((Dht01_Hbps(hbps) | Dht01_Ht(ht)), DHT01);
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write_reg_dly((Dht02_Hlbs(has) | Dht02_Has(has)), DHT02);
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write_reg_dly((Dht03_Hfps(hfps) | Dht03_Hrbs(hfps)), DHT03);
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write_reg_dly((Dhdet_Hdes(has) | Dhdet_Hdef(hfps)), DHDET);
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writel((Dvt01_Vbps(vbps) | Dvt01_Vt(vt)), DVT01);
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writel((Dvt02_Vtbs(vas) | Dvt02_Vas(vas)), DVT02);
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writel((Dvt03_Vfps(vfps) | Dvt03_Vbbs(vfps)), DVT03);
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writel((Dvdet_Vdes(vas) | Dvdet_Vdef(vfps)), DVDET);
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writel((Dvectrl_Vevent(vfps) | Dvectrl_Vfetch(vbps)), DVECTRL);
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write_reg_dly((Dvt01_Vbps(vbps) | Dvt01_Vt(vt)), DVT01);
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write_reg_dly((Dvt02_Vtbs(vas) | Dvt02_Vas(vas)), DVT02);
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write_reg_dly((Dvt03_Vfps(vfps) | Dvt03_Vbbs(vfps)), DVT03);
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write_reg_dly((Dvdet_Vdes(vas) | Dvdet_Vdef(vfps)), DVDET);
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write_reg_dly((Dvectrl_Vevent(vfps) | Dvectrl_Vfetch(vbps)), DVECTRL);
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writel((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
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write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
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write_reg_dly(DINTRE_VEVENT0_EN, DINTRE);
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return 0;
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}
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@ -305,23 +320,203 @@ static int mbxfb_blank(int blank, struct fb_info *info)
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case FB_BLANK_VSYNC_SUSPEND:
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case FB_BLANK_HSYNC_SUSPEND:
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case FB_BLANK_NORMAL:
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writel((readl(DSCTRL) & ~DSCTRL_SYNCGEN_EN), DSCTRL);
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udelay(1000);
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writel((readl(PIXCLK) & ~PIXCLK_EN), PIXCLK);
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udelay(1000);
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writel((readl(VOVRCLK) & ~VOVRCLK_EN), VOVRCLK);
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udelay(1000);
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write_reg_dly((readl(DSCTRL) & ~DSCTRL_SYNCGEN_EN), DSCTRL);
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write_reg_dly((readl(PIXCLK) & ~PIXCLK_EN), PIXCLK);
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write_reg_dly((readl(VOVRCLK) & ~VOVRCLK_EN), VOVRCLK);
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break;
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case FB_BLANK_UNBLANK:
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writel((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
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udelay(1000);
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writel((readl(PIXCLK) | PIXCLK_EN), PIXCLK);
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udelay(1000);
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write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
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write_reg_dly((readl(PIXCLK) | PIXCLK_EN), PIXCLK);
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break;
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}
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return 0;
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}
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static int mbxfb_setupOverlay(struct mbxfb_overlaySetup *set)
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{
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u32 vsctrl, vbbase, vscadr, vsadr;
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u32 sssize, spoctrl, svctrl, shctrl;
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u32 vubase, vvbase;
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u32 vovrclk;
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if (set->scaled_width==0 || set->scaled_height==0)
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return -EINVAL;
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/* read registers which have reserved bits
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* so we can write them back as-is. */
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vovrclk = readl(VOVRCLK);
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vsctrl = readl(VSCTRL);
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vscadr = readl(VSCADR);
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vubase = readl(VUBASE);
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vvbase = readl(VVBASE);
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spoctrl = readl(SPOCTRL);
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sssize = readl(SSSIZE);
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vbbase = Vbbase_Glalpha(set->alpha);
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vsctrl &= ~( FMsk(VSCTRL_VSWIDTH) |
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FMsk(VSCTRL_VSHEIGHT) |
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FMsk(VSCTRL_VPIXFMT) |
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VSCTRL_GAMMA_EN | VSCTRL_CSC_EN |
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VSCTRL_COSITED );
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vsctrl |= Vsctrl_Width(set->width) | Vsctrl_Height(set->height) |
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VSCTRL_CSC_EN;
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vscadr &= ~(VSCADR_STR_EN | VSCADR_COLKEY_EN | VSCADR_COLKEYSRC |
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FMsk(VSCADR_BLEND_M) | FMsk(VSCADR_BLEND_POS) |
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FMsk(VSCADR_VBASE_ADR) );
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vubase &= ~(VUBASE_UVHALFSTR | FMsk(VUBASE_UBASE_ADR));
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vvbase &= ~(FMsk(VVBASE_VBASE_ADR));
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switch (set->fmt)
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{
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case MBXFB_FMT_YUV12:
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vsctrl |= VSCTRL_VPIXFMT_YUV12;
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set->Y_stride = ((set->width) + 0xf ) & ~0xf;
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break;
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case MBXFB_FMT_UY0VY1:
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vsctrl |= VSCTRL_VPIXFMT_UY0VY1;
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set->Y_stride = (set->width*2 + 0xf ) & ~0xf;
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break;
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case MBXFB_FMT_VY0UY1:
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vsctrl |= VSCTRL_VPIXFMT_VY0UY1;
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set->Y_stride = (set->width*2 + 0xf ) & ~0xf;
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break;
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case MBXFB_FMT_Y0UY1V:
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vsctrl |= VSCTRL_VPIXFMT_Y0UY1V;
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set->Y_stride = (set->width*2 + 0xf ) & ~0xf;
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break;
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case MBXFB_FMT_Y0VY1U:
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vsctrl |= VSCTRL_VPIXFMT_Y0VY1U;
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set->Y_stride = (set->width*2 + 0xf ) & ~0xf;
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break;
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default:
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return -EINVAL;
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}
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/* VSCTRL has the bits which sets the Video Pixel Format.
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* When passing from a packed to planar format,
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* if we write VSCTRL first, VVBASE and VUBASE would
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* be zero if we would not set them here. (And then,
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* the chips hangs and only a reset seems to fix it).
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*
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* If course, the values calculated here have no meaning
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* for packed formats.
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*/
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set->UV_stride = ((set->width/2) + 0x7 ) & ~0x7;
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set->U_offset = set->height * set->Y_stride;
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set->V_offset = set->U_offset +
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set->height * set->UV_stride;
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vubase |= Vubase_Ubase_Adr(
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(0x60000 + set->mem_offset + set->U_offset)>>3);
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vvbase |= Vvbase_Vbase_Adr(
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(0x60000 + set->mem_offset + set->V_offset)>>3);
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vscadr |= VSCADR_BLEND_VID | VSCADR_BLEND_GLOB |
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Vscadr_Vbase_Adr((0x60000 + set->mem_offset)>>4);
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if (set->enable)
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vscadr |= VSCADR_STR_EN;
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vsadr = Vsadr_Srcstride((set->Y_stride)/16-1) |
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Vsadr_Xstart(set->x) | Vsadr_Ystart(set->y);
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sssize &= ~(FMsk(SSSIZE_SC_WIDTH) | FMsk(SSSIZE_SC_HEIGHT));
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sssize = Sssize_Sc_Width(set->scaled_width-1) |
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Sssize_Sc_Height(set->scaled_height-1);
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spoctrl &= ~(SPOCTRL_H_SC_BP | SPOCTRL_V_SC_BP |
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SPOCTRL_HV_SC_OR | SPOCTRL_VS_UR_C |
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FMsk(SPOCTRL_VORDER) | FMsk(SPOCTRL_VPITCH));
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spoctrl = Spoctrl_Vpitch((set->height<<11)/set->scaled_height)
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| SPOCTRL_VORDER_2TAP;
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/* Bypass horiz/vert scaler when same size */
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if (set->scaled_width == set->width)
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spoctrl |= SPOCTRL_H_SC_BP;
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if (set->scaled_height == set->height)
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spoctrl |= SPOCTRL_V_SC_BP;
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svctrl = Svctrl_Initial1(1<<10) | Svctrl_Initial2(1<<10);
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shctrl = Shctrl_Hinitial(4<<11)
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| Shctrl_Hpitch((set->width<<11)/set->scaled_width);
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/* Video plane registers */
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write_reg(vsctrl, VSCTRL);
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write_reg(vbbase, VBBASE);
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write_reg(vscadr, VSCADR);
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write_reg(vubase, VUBASE);
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write_reg(vvbase, VVBASE);
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write_reg(vsadr, VSADR);
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/* Video scaler registers */
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write_reg(sssize, SSSIZE);
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write_reg(spoctrl, SPOCTRL);
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write_reg(svctrl, SVCTRL);
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write_reg(shctrl, SHCTRL);
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/* RAPH: Using those coefficients, the scaled
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* image is quite blurry. I dont know how
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* to improve them ; The chip documentation
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* was not helpful.. */
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write_reg(0x21212121, VSCOEFF0);
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write_reg(0x21212121, VSCOEFF1);
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write_reg(0x21212121, VSCOEFF2);
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write_reg(0x21212121, VSCOEFF3);
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write_reg(0x21212121, VSCOEFF4);
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write_reg(0x00000000, HSCOEFF0);
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write_reg(0x00000000, HSCOEFF1);
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write_reg(0x00000000, HSCOEFF2);
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write_reg(0x03020201, HSCOEFF3);
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write_reg(0x09070604, HSCOEFF4);
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write_reg(0x0f0e0c0a, HSCOEFF5);
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write_reg(0x15141211, HSCOEFF6);
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write_reg(0x19181716, HSCOEFF7);
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write_reg(0x00000019, HSCOEFF8);
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/* Clock */
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if (set->enable)
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vovrclk |= 1;
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else
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vovrclk &= ~1;
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write_reg(vovrclk, VOVRCLK);
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return 0;
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}
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static int mbxfb_ioctl(struct fb_info *info, unsigned int cmd,
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unsigned long arg)
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{
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struct mbxfb_overlaySetup setup;
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int res;
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if (cmd == MBXFB_IOCX_OVERLAY)
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{
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if (copy_from_user(&setup, (void __user*)arg,
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sizeof(struct mbxfb_overlaySetup)))
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return -EFAULT;
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res = mbxfb_setupOverlay(&setup);
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if (res)
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return res;
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if (copy_to_user((void __user*)arg, &setup,
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sizeof(struct mbxfb_overlaySetup)))
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return -EFAULT;
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return 0;
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}
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return -EINVAL;
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}
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static struct fb_ops mbxfb_ops = {
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.owner = THIS_MODULE,
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.fb_check_var = mbxfb_check_var,
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@ -331,6 +526,7 @@ static struct fb_ops mbxfb_ops = {
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.fb_copyarea = cfb_copyarea,
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.fb_imageblit = cfb_imageblit,
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.fb_blank = mbxfb_blank,
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.fb_ioctl = mbxfb_ioctl,
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};
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/*
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@ -339,36 +535,29 @@ static struct fb_ops mbxfb_ops = {
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*/
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static void __devinit setup_memc(struct fb_info *fbi)
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{
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struct mbxfb_info *mfbi = fbi->par;
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unsigned long tmp;
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int i;
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/* FIXME: use platfrom specific parameters */
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/* setup SDRAM controller */
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writel((LMCFG_LMC_DS | LMCFG_LMC_TS | LMCFG_LMD_TS |
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write_reg_dly((LMCFG_LMC_DS | LMCFG_LMC_TS | LMCFG_LMD_TS |
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LMCFG_LMA_TS),
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LMCFG);
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udelay(1000);
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writel(LMPWR_MC_PWR_ACT, LMPWR);
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udelay(1000);
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write_reg_dly(LMPWR_MC_PWR_ACT, LMPWR);
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/* setup SDRAM timings */
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writel((Lmtim_Tras(7) | Lmtim_Trp(3) | Lmtim_Trcd(3) |
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write_reg_dly((Lmtim_Tras(7) | Lmtim_Trp(3) | Lmtim_Trcd(3) |
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Lmtim_Trc(9) | Lmtim_Tdpl(2)),
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LMTIM);
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udelay(1000);
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/* setup SDRAM refresh rate */
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writel(0xc2b, LMREFRESH);
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udelay(1000);
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write_reg_dly(0xc2b, LMREFRESH);
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/* setup SDRAM type parameters */
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writel((LMTYPE_CASLAT_3 | LMTYPE_BKSZ_2 | LMTYPE_ROWSZ_11 |
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write_reg_dly((LMTYPE_CASLAT_3 | LMTYPE_BKSZ_2 | LMTYPE_ROWSZ_11 |
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LMTYPE_COLSZ_8),
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LMTYPE);
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udelay(1000);
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/* enable memory controller */
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writel(LMPWR_MC_PWR_ACT, LMPWR);
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udelay(1000);
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write_reg_dly(LMPWR_MC_PWR_ACT, LMPWR);
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/* perform dummy reads */
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for ( i = 0; i < 16; i++ ) {
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@ -379,34 +568,30 @@ static void __devinit setup_memc(struct fb_info *fbi)
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static void enable_clocks(struct fb_info *fbi)
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{
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/* enable clocks */
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writel(SYSCLKSRC_PLL_2, SYSCLKSRC);
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udelay(1000);
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writel(PIXCLKSRC_PLL_1, PIXCLKSRC);
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udelay(1000);
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writel(0x00000000, CLKSLEEP);
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udelay(1000);
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writel((Core_Pll_M(0x17) | Core_Pll_N(0x3) | Core_Pll_P(0x0) |
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write_reg_dly(SYSCLKSRC_PLL_2, SYSCLKSRC);
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write_reg_dly(PIXCLKSRC_PLL_1, PIXCLKSRC);
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write_reg_dly(0x00000000, CLKSLEEP);
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/* PLL output = (Frefclk * M) / (N * 2^P )
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*
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* M: 0x17, N: 0x3, P: 0x0 == 100 Mhz!
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* M: 0xb, N: 0x1, P: 0x1 == 71 Mhz
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* */
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write_reg_dly((Core_Pll_M(0xb) | Core_Pll_N(0x1) | Core_Pll_P(0x1) |
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CORE_PLL_EN),
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COREPLL);
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udelay(1000);
|
||||
writel((Disp_Pll_M(0x1b) | Disp_Pll_N(0x7) | Disp_Pll_P(0x1) |
|
||||
|
||||
write_reg_dly((Disp_Pll_M(0x1b) | Disp_Pll_N(0x7) | Disp_Pll_P(0x1) |
|
||||
DISP_PLL_EN),
|
||||
DISPPLL);
|
||||
|
||||
writel(0x00000000, VOVRCLK);
|
||||
udelay(1000);
|
||||
writel(PIXCLK_EN, PIXCLK);
|
||||
udelay(1000);
|
||||
writel(MEMCLK_EN, MEMCLK);
|
||||
udelay(1000);
|
||||
writel(0x00000006, M24CLK);
|
||||
udelay(1000);
|
||||
writel(0x00000006, MBXCLK);
|
||||
udelay(1000);
|
||||
writel(SDCLK_EN, SDCLK);
|
||||
udelay(1000);
|
||||
writel(0x00000001, PIXCLKDIV);
|
||||
udelay(1000);
|
||||
write_reg_dly(0x00000000, VOVRCLK);
|
||||
write_reg_dly(PIXCLK_EN, PIXCLK);
|
||||
write_reg_dly(MEMCLK_EN, MEMCLK);
|
||||
write_reg_dly(0x00000006, M24CLK);
|
||||
write_reg_dly(0x00000006, MBXCLK);
|
||||
write_reg_dly(SDCLK_EN, SDCLK);
|
||||
write_reg_dly(0x00000001, PIXCLKDIV);
|
||||
}
|
||||
|
||||
static void __devinit setup_graphics(struct fb_info *fbi)
|
||||
|
|
@ -430,16 +615,11 @@ static void __devinit setup_graphics(struct fb_info *fbi)
|
|||
break;
|
||||
}
|
||||
|
||||
writel(gsctrl, GSCTRL);
|
||||
udelay(1000);
|
||||
writel(0x00000000, GBBASE);
|
||||
udelay(1000);
|
||||
writel(0x00ffffff, GDRCTRL);
|
||||
udelay(1000);
|
||||
writel((GSCADR_STR_EN | Gscadr_Gbase_Adr(0x6000)), GSCADR);
|
||||
udelay(1000);
|
||||
writel(0x00000000, GPLUT);
|
||||
udelay(1000);
|
||||
write_reg_dly(gsctrl, GSCTRL);
|
||||
write_reg_dly(0x00000000, GBBASE);
|
||||
write_reg_dly(0x00ffffff, GDRCTRL);
|
||||
write_reg_dly((GSCADR_STR_EN | Gscadr_Gbase_Adr(0x6000)), GSCADR);
|
||||
write_reg_dly(0x00000000, GPLUT);
|
||||
}
|
||||
|
||||
static void __devinit setup_display(struct fb_info *fbi)
|
||||
|
|
@ -451,17 +631,14 @@ static void __devinit setup_display(struct fb_info *fbi)
|
|||
dsctrl |= DSCTRL_HS_POL;
|
||||
if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
|
||||
dsctrl |= DSCTRL_VS_POL;
|
||||
writel(dsctrl, DSCTRL);
|
||||
udelay(1000);
|
||||
writel(0xd0303010, DMCTRL);
|
||||
udelay(1000);
|
||||
writel((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
|
||||
write_reg_dly(dsctrl, DSCTRL);
|
||||
write_reg_dly(0xd0303010, DMCTRL);
|
||||
write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
|
||||
}
|
||||
|
||||
static void __devinit enable_controller(struct fb_info *fbi)
|
||||
{
|
||||
writel(SYSRST_RST, SYSRST);
|
||||
udelay(1000);
|
||||
write_reg_dly(SYSRST_RST, SYSRST);
|
||||
|
||||
|
||||
enable_clocks(fbi);
|
||||
|
|
@ -478,12 +655,12 @@ static void __devinit enable_controller(struct fb_info *fbi)
|
|||
static int mbxfb_suspend(struct platform_device *dev, pm_message_t state)
|
||||
{
|
||||
/* make frame buffer memory enter self-refresh mode */
|
||||
writel(LMPWR_MC_PWR_SRM, LMPWR);
|
||||
write_reg_dly(LMPWR_MC_PWR_SRM, LMPWR);
|
||||
while (LMPWRSTAT != LMPWRSTAT_MC_PWR_SRM)
|
||||
; /* empty statement */
|
||||
|
||||
/* reset the device, since it's initial state is 'mostly sleeping' */
|
||||
writel(SYSRST_RST, SYSRST);
|
||||
write_reg_dly(SYSRST_RST, SYSRST);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -495,7 +672,7 @@ static int mbxfb_resume(struct platform_device *dev)
|
|||
/* setup_graphics(fbi); */
|
||||
/* setup_display(fbi); */
|
||||
|
||||
writel((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
|
||||
write_reg_dly((readl(DSCTRL) | DSCTRL_SYNCGEN_EN), DSCTRL);
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
|
|
@ -520,6 +697,12 @@ static int __devinit mbxfb_probe(struct platform_device *dev)
|
|||
|
||||
dev_dbg(dev, "mbxfb_probe\n");
|
||||
|
||||
pdata = dev->dev.platform_data;
|
||||
if (!pdata) {
|
||||
dev_err(&dev->dev, "platform data is required\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
fbi = framebuffer_alloc(sizeof(struct mbxfb_info), &dev->dev);
|
||||
if (fbi == NULL) {
|
||||
dev_err(&dev->dev, "framebuffer_alloc failed\n");
|
||||
|
|
@ -528,7 +711,8 @@ static int __devinit mbxfb_probe(struct platform_device *dev)
|
|||
|
||||
mfbi = fbi->par;
|
||||
fbi->pseudo_palette = mfbi->pseudo_palette;
|
||||
pdata = dev->dev.platform_data;
|
||||
|
||||
|
||||
if (pdata->probe)
|
||||
mfbi->platform_probe = pdata->probe;
|
||||
if (pdata->remove)
|
||||
|
|
@ -578,16 +762,16 @@ static int __devinit mbxfb_probe(struct platform_device *dev)
|
|||
goto err4;
|
||||
}
|
||||
|
||||
/* FIXME: get from platform */
|
||||
fbi->screen_base = (char __iomem *)(mfbi->fb_virt_addr + 0x60000);
|
||||
fbi->screen_size = 8 * 1024 * 1024; /* 8 Megs */
|
||||
fbi->screen_size = pdata->memsize;
|
||||
fbi->fbops = &mbxfb_ops;
|
||||
|
||||
fbi->var = mbxfb_default;
|
||||
fbi->fix = mbxfb_fix;
|
||||
fbi->fix.smem_start = mfbi->fb_phys_addr + 0x60000;
|
||||
fbi->fix.smem_len = 8 * 1024 * 1024;
|
||||
fbi->fix.line_length = 640 * 2;
|
||||
fbi->fix.smem_len = pdata->memsize;
|
||||
fbi->fix.line_length = mbxfb_default.xres_virtual *
|
||||
mbxfb_default.bits_per_pixel / 8;
|
||||
|
||||
ret = fb_alloc_cmap(&fbi->cmap, 256, 0);
|
||||
if (ret < 0) {
|
||||
|
|
@ -636,8 +820,7 @@ static int __devexit mbxfb_remove(struct platform_device *dev)
|
|||
{
|
||||
struct fb_info *fbi = platform_get_drvdata(dev);
|
||||
|
||||
writel(SYSRST_RST, SYSRST);
|
||||
udelay(1000);
|
||||
write_reg_dly(SYSRST_RST, SYSRST);
|
||||
|
||||
mbxfb_debugfs_remove(fbi);
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,9 @@
|
|||
#ifndef __MBX_FB_H
|
||||
#define __MBX_FB_H
|
||||
|
||||
#include <asm/ioctl.h>
|
||||
#include <asm/types.h>
|
||||
|
||||
struct mbxfb_val {
|
||||
unsigned int defval;
|
||||
unsigned int min;
|
||||
|
|
@ -25,4 +28,32 @@ struct mbxfb_platform_data {
|
|||
int (*remove)(struct fb_info *fb);
|
||||
};
|
||||
|
||||
/* planar */
|
||||
#define MBXFB_FMT_YUV12 0
|
||||
|
||||
/* packed */
|
||||
#define MBXFB_FMT_UY0VY1 1
|
||||
#define MBXFB_FMT_VY0UY1 2
|
||||
#define MBXFB_FMT_Y0UY1V 3
|
||||
#define MBXFB_FMT_Y0VY1U 4
|
||||
struct mbxfb_overlaySetup {
|
||||
__u32 enable;
|
||||
__u32 x, y;
|
||||
__u32 width, height;
|
||||
__u32 alpha;
|
||||
__u32 fmt;
|
||||
__u32 mem_offset;
|
||||
__u32 scaled_width;
|
||||
__u32 scaled_height;
|
||||
|
||||
/* Filled by the driver */
|
||||
__u32 U_offset;
|
||||
__u32 V_offset;
|
||||
|
||||
__u16 Y_stride;
|
||||
__u16 UV_stride;
|
||||
};
|
||||
|
||||
#define MBXFB_IOCX_OVERLAY _IOWR(0xF4, 0x00,struct mbxfb_overlaySetup)
|
||||
|
||||
#endif /* __MBX_FB_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue