From 372401efd9eeee24701848874ecb9845524013ee Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Tue, 22 May 2018 18:34:56 +0200 Subject: [PATCH 1/9] dt-bindings: clock: add meson axg audio clock controller bindings Export the clock ids dt-bindings usable by the consumers of the clock controller and add the documentation for the device tree bindings of the audio clock controller of the A113 based SoCs. Acked-by: Neil Armstrong Reviewed-by: Rob Herring Signed-off-by: Jerome Brunet --- .../bindings/clock/amlogic,axg-audio-clkc.txt | 56 +++++++++++ include/dt-bindings/clock/axg-audio-clkc.h | 94 +++++++++++++++++++ 2 files changed, 150 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt create mode 100644 include/dt-bindings/clock/axg-audio-clkc.h diff --git a/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt new file mode 100644 index 000000000000..61777ad24f61 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/amlogic,axg-audio-clkc.txt @@ -0,0 +1,56 @@ +* Amlogic AXG Audio Clock Controllers + +The Amlogic AXG audio clock controller generates and supplies clock to the +other elements of the audio subsystem, such as fifos, i2s, spdif and pdm +devices. + +Required Properties: + +- compatible : should be "amlogic,axg-audio-clkc" for the A113X and A113D +- reg : physical base address of the clock controller and length of + memory mapped region. +- clocks : a list of phandle + clock-specifier pairs for the clocks listed + in clock-names. +- clock-names : must contain the following: + * "pclk" - Main peripheral bus clock + may contain the following: + * "mst_in[0-7]" - 8 input plls to generate clock signals + * "slv_sclk[0-9]" - 10 slave bit clocks provided by external + components. + * "slv_lrclk[0-9]" - 10 slave sample clocks provided by external + components. +- resets : phandle of the internal reset line +- #clock-cells : should be 1. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/axg-audio-clkc.h header and can be +used in device tree sources. + +Example: + +clkc_audio: clock-controller@0 { + compatible = "amlogic,axg-audio-clkc"; + reg = <0x0 0x0 0x0 0xb4>; + #clock-cells = <1>; + + clocks = <&clkc CLKID_AUDIO>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL3>, + <&clkc CLKID_HIFI_PLL>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_GP0_PLL>; + clock-names = "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4", + "mst_in5", + "mst_in6", + "mst_in7"; + resets = <&reset RESET_AUDIO>; +}; diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h new file mode 100644 index 000000000000..fd9c362099d9 --- /dev/null +++ b/include/dt-bindings/clock/axg-audio-clkc.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* + * Copyright (c) 2018 Baylibre SAS. + * Author: Jerome Brunet + */ + +#ifndef __AXG_AUDIO_CLKC_BINDINGS_H +#define __AXG_AUDIO_CLKC_BINDINGS_H + +#define AUD_CLKID_SLV_SCLK0 9 +#define AUD_CLKID_SLV_SCLK1 10 +#define AUD_CLKID_SLV_SCLK2 11 +#define AUD_CLKID_SLV_SCLK3 12 +#define AUD_CLKID_SLV_SCLK4 13 +#define AUD_CLKID_SLV_SCLK5 14 +#define AUD_CLKID_SLV_SCLK6 15 +#define AUD_CLKID_SLV_SCLK7 16 +#define AUD_CLKID_SLV_SCLK8 17 +#define AUD_CLKID_SLV_SCLK9 18 +#define AUD_CLKID_SLV_LRCLK0 19 +#define AUD_CLKID_SLV_LRCLK1 20 +#define AUD_CLKID_SLV_LRCLK2 21 +#define AUD_CLKID_SLV_LRCLK3 22 +#define AUD_CLKID_SLV_LRCLK4 23 +#define AUD_CLKID_SLV_LRCLK5 24 +#define AUD_CLKID_SLV_LRCLK6 25 +#define AUD_CLKID_SLV_LRCLK7 26 +#define AUD_CLKID_SLV_LRCLK8 27 +#define AUD_CLKID_SLV_LRCLK9 28 +#define AUD_CLKID_DDR_ARB 29 +#define AUD_CLKID_PDM 30 +#define AUD_CLKID_TDMIN_A 31 +#define AUD_CLKID_TDMIN_B 32 +#define AUD_CLKID_TDMIN_C 33 +#define AUD_CLKID_TDMIN_LB 34 +#define AUD_CLKID_TDMOUT_A 35 +#define AUD_CLKID_TDMOUT_B 36 +#define AUD_CLKID_TDMOUT_C 37 +#define AUD_CLKID_FRDDR_A 38 +#define AUD_CLKID_FRDDR_B 39 +#define AUD_CLKID_FRDDR_C 40 +#define AUD_CLKID_TODDR_A 41 +#define AUD_CLKID_TODDR_B 42 +#define AUD_CLKID_TODDR_C 43 +#define AUD_CLKID_LOOPBACK 44 +#define AUD_CLKID_SPDIFIN 45 +#define AUD_CLKID_SPDIFOUT 46 +#define AUD_CLKID_RESAMPLE 47 +#define AUD_CLKID_POWER_DETECT 48 +#define AUD_CLKID_MST_A_MCLK 49 +#define AUD_CLKID_MST_B_MCLK 50 +#define AUD_CLKID_MST_C_MCLK 51 +#define AUD_CLKID_MST_D_MCLK 52 +#define AUD_CLKID_MST_E_MCLK 53 +#define AUD_CLKID_MST_F_MCLK 54 +#define AUD_CLKID_SPDIFOUT_CLK 55 +#define AUD_CLKID_SPDIFIN_CLK 56 +#define AUD_CLKID_PDM_DCLK 57 +#define AUD_CLKID_PDM_SYSCLK 58 +#define AUD_CLKID_MST_A_SCLK 79 +#define AUD_CLKID_MST_B_SCLK 80 +#define AUD_CLKID_MST_C_SCLK 81 +#define AUD_CLKID_MST_D_SCLK 82 +#define AUD_CLKID_MST_E_SCLK 83 +#define AUD_CLKID_MST_F_SCLK 84 +#define AUD_CLKID_MST_A_LRCLK 86 +#define AUD_CLKID_MST_B_LRCLK 87 +#define AUD_CLKID_MST_C_LRCLK 88 +#define AUD_CLKID_MST_D_LRCLK 89 +#define AUD_CLKID_MST_E_LRCLK 90 +#define AUD_CLKID_MST_F_LRCLK 91 +#define AUD_CLKID_TDMIN_A_SCLK_SEL 116 +#define AUD_CLKID_TDMIN_B_SCLK_SEL 117 +#define AUD_CLKID_TDMIN_C_SCLK_SEL 118 +#define AUD_CLKID_TDMIN_LB_SCLK_SEL 119 +#define AUD_CLKID_TDMOUT_A_SCLK_SEL 120 +#define AUD_CLKID_TDMOUT_B_SCLK_SEL 121 +#define AUD_CLKID_TDMOUT_C_SCLK_SEL 122 +#define AUD_CLKID_TDMIN_A_SCLK 123 +#define AUD_CLKID_TDMIN_B_SCLK 124 +#define AUD_CLKID_TDMIN_C_SCLK 125 +#define AUD_CLKID_TDMIN_LB_SCLK 126 +#define AUD_CLKID_TDMOUT_A_SCLK 127 +#define AUD_CLKID_TDMOUT_B_SCLK 128 +#define AUD_CLKID_TDMOUT_C_SCLK 129 +#define AUD_CLKID_TDMIN_A_LRCLK 130 +#define AUD_CLKID_TDMIN_B_LRCLK 131 +#define AUD_CLKID_TDMIN_C_LRCLK 132 +#define AUD_CLKID_TDMIN_LB_LRCLK 133 +#define AUD_CLKID_TDMOUT_A_LRCLK 134 +#define AUD_CLKID_TDMOUT_B_LRCLK 135 +#define AUD_CLKID_TDMOUT_C_LRCLK 136 + +#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */ From 6c0ad1df179b8d26ecd5e9954c36146fa87c1b0c Mon Sep 17 00:00:00 2001 From: Yixun Lan Date: Mon, 2 Jul 2018 21:31:17 +0000 Subject: [PATCH 2/9] clk: meson-axg: add pcie and mipi clock bindings Add the pcie and mipi clock dt-bindings for the pcie driver. Since the mipi clock isalso used by the pcie driver, we add it together in this patch. Tested-by: Jianxin Qin Signed-off-by: Yixun Lan Signed-off-by: Jerome Brunet --- include/dt-bindings/clock/axg-clkc.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h index 555937a25504..70371228b7e0 100644 --- a/include/dt-bindings/clock/axg-clkc.h +++ b/include/dt-bindings/clock/axg-clkc.h @@ -68,5 +68,8 @@ #define CLKID_SD_EMMC_B_CLK0 59 #define CLKID_SD_EMMC_C_CLK0 60 #define CLKID_HIFI_PLL 69 +#define CLKID_PCIE_CML_EN0 79 +#define CLKID_PCIE_CML_EN1 80 +#define CLKID_MIPI_ENABLE 81 #endif /* __AXG_CLKC_H */ From de3c1e71d412d7e254e3eebeb82e260fb8513566 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Wed, 4 Jul 2018 18:54:57 +0200 Subject: [PATCH 3/9] clk: meson: expose GEN_CLK clkid Expose GEN_CLK clock id Signed-off-by: Jerome Brunet --- include/dt-bindings/clock/axg-clkc.h | 1 + include/dt-bindings/clock/gxbb-clkc.h | 1 + 2 files changed, 2 insertions(+) diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h index 70371228b7e0..fd1f938c38d1 100644 --- a/include/dt-bindings/clock/axg-clkc.h +++ b/include/dt-bindings/clock/axg-clkc.h @@ -71,5 +71,6 @@ #define CLKID_PCIE_CML_EN0 79 #define CLKID_PCIE_CML_EN1 80 #define CLKID_MIPI_ENABLE 81 +#define CLKID_GEN_CLK 84 #endif /* __AXG_CLKC_H */ diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h index 7a892be90549..3979d48c025f 100644 --- a/include/dt-bindings/clock/gxbb-clkc.h +++ b/include/dt-bindings/clock/gxbb-clkc.h @@ -127,5 +127,6 @@ #define CLKID_VAPB 140 #define CLKID_VDEC_1 153 #define CLKID_VDEC_HEVC 156 +#define CLKID_GEN_CLK 159 #endif /* __GXBB_CLKC_H */ From 8909e72270f20ff53c9c3de86e7b69c2a5e20074 Mon Sep 17 00:00:00 2001 From: Jerome Brunet Date: Mon, 16 Jul 2018 12:11:51 +0200 Subject: [PATCH 4/9] ARM64: dts: meson-axg: add the audio clock controller Add the audio clock controller which is part of the audio bus This controller takes 8 input plls, and the usual clock gate, from the main clock controller. It provides the clocs for the all the devices of the audio subsystem, such as tdms, spdif, pdm, etc. Signed-off-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi index 245039bd0d5a..11589469fb1d 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -155,6 +156,41 @@ sd_emmc_c: mmc@7000 { }; }; + audio: bus@ff642000 { + compatible = "simple-bus"; + reg = <0x0 0xff642000 0x0 0x2000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; + + clkc_audio: clock-controller@0 { + compatible = "amlogic,axg-audio-clkc"; + reg = <0x0 0x0 0x0 0xb4>; + #clock-cells = <1>; + + clocks = <&clkc CLKID_AUDIO>, + <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>, + <&clkc CLKID_MPLL3>, + <&clkc CLKID_HIFI_PLL>, + <&clkc CLKID_FCLK_DIV3>, + <&clkc CLKID_FCLK_DIV4>, + <&clkc CLKID_GP0_PLL>; + clock-names = "pclk", + "mst_in0", + "mst_in1", + "mst_in2", + "mst_in3", + "mst_in4", + "mst_in5", + "mst_in6", + "mst_in7"; + + resets = <&reset RESET_AUDIO>; + }; + }; + cbus: bus@ffd00000 { compatible = "simple-bus"; reg = <0x0 0xffd00000 0x0 0x25000>; From 405f69b4492772951390ea8708101ba963dc471a Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 14 Jul 2018 21:37:21 +0200 Subject: [PATCH 5/9] dt-bindings: add vendor prefix for Shenzhen Oranth Technology Co., Ltd. According to their website (http://www.oranth.com/about-oranth/) Shenzhen Oranth Technology Co., Ltd. (or simply "Oranth") "is a professional Design House & Manufacturer for Android TV Box established in 2014". One of their brands is Tanix (sometimes also spelled "TANIX"). One of their most popular devices is the "Tanix TX3 Mini" TV box (which uses the Amlogic S905W chipset). Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/vendor-prefixes.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index 7cad066191ee..5b9a96d863ee 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -271,6 +271,7 @@ opalkelly Opal Kelly Incorporated opencores OpenCores.org openrisc OpenRISC.io option Option NV +oranth Shenzhen Oranth Technology Co., Ltd. ORCL Oracle Corporation orisetech Orise Technology ortustech Ortus Technology Co., Ltd. From 580f1f41bf090755a32c229e2ea2c2db86f6eab1 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 14 Jul 2018 21:37:22 +0200 Subject: [PATCH 6/9] dt-bindings: arm: amlogic: Add support for GXL S905W and the P281 board S905W SoC is another SoC from the GXL family. It is a cost-reduced version of the S905X SoC. The following differences are known: - S905W supports HDMI resolutions up to 4k@30fps (while S905X support resolutions up to 4k@60fps) - the built-in video decoders of S905W decode up to 4k@30fps (while S905X supports decoding up to 4k@60fps) - CPU speed on S905W is limited to 1.2GHz (compared to 1.5GHz on S905X, this is handled in the SCPI firmware) - the DRAM interface on S905W is limited to 16-bit (GXL supports both, 16-bit and 32-bit) Notes based on Amlogic's GPL kernel sources: - the P281 is a development board from Amlogic which uses the S905W SoC. Amlogic's GPL kernel sources indicate that it uses the same PCB layout as the "P231" board (and simply replaces the S905D from the original P231 board with a S905W SoC). - it is assumed that the S905W SoC is pin-compatible with the S905X SoC since Amlogic's GPL kernel sources use the same driver for both SoCs. - gxl_p281_1g.dts contains a comment which mentions that "max gp pll for gpu is 650M, temporarily disabled". However, it seems to boot fine with 744MHz (as used on GXBB and the other GXL SoCs). Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 849834cb1766..8178da8742c3 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -45,6 +45,10 @@ Boards with the Amlogic Meson GXL S805X SoC shall have the following properties: Required root node property: compatible: "amlogic,s805x", "amlogic,meson-gxl"; +Boards with the Amlogic Meson GXL S905W SoC shall have the following properties: + Required root node property: + compatible: "amlogic,s905w", "amlogic,meson-gxl"; + Boards with the Amlogic Meson GXM S912 SoC shall have the following properties: Required root node property: compatible: "amlogic,s912", "amlogic,meson-gxm"; @@ -85,6 +89,8 @@ Board compatible values (alphabetically, grouped by SoC): - "amlogic,p241" (Meson gxl s805x) + - "amlogic,p281" (Meson gxl s905w) + - "amlogic,q200" (Meson gxm s912) - "amlogic,q201" (Meson gxm s912) - "khadas,vim2" (Meson gxm s912) From d6996e3cbd16751b7518d7061ad4710d78bc0646 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 14 Jul 2018 21:37:23 +0200 Subject: [PATCH 7/9] dt-bindings: arm: amlogic: Add support for the Oranth Tanix TX3 Mini The Tanix TX3 Mini is a TV box based on the Amlogic S905W chipset. It comes with: - 1 GiB or 2 GiB of DDR3 memory depending on the model - 8 GB or 16 GB eMMC flash depending on the model - 802.11 b/g/n wifi (Silicon Valley Microelectronics SSV6051, does not support Bluetooth, not supported by any mailine driver) - an LED 7 segment display with an FD628 controller (not supported by any mainline driver) - HDMI and AV (CVBS) output - 2x USB (utilizing both USB ports provided by the SoC) - micro SD card slot The board seems to be very similar to the P23x and Q20x reference boards: - eMMC reset routed to BOOT_9 - the SDIO wifi chip's reset line is routed to GPIOX_6 and the reference clock is 32.768KHz on PWM_E - SD card detection is routed to CARD_6 - vqmmc of all MMC controllers is hard-wired to 1.8V (VDDIO_BOOT) - uart_AO can be accessed after opening the case and soldering RX, TX and GND lines onto the exposed solder points (marked with RX, TX and GND) Signed-off-by: Martin Blumenstingl Reviewed-by: Rob Herring Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- Documentation/devicetree/bindings/arm/amlogic.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt index 8178da8742c3..b5c2b5c35766 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.txt +++ b/Documentation/devicetree/bindings/arm/amlogic.txt @@ -90,6 +90,7 @@ Board compatible values (alphabetically, grouped by SoC): - "amlogic,p241" (Meson gxl s805x) - "amlogic,p281" (Meson gxl s905w) + - "oranth,tx3-mini" (Meson gxl s905w) - "amlogic,q200" (Meson gxm s912) - "amlogic,q201" (Meson gxm s912) From e3b8b7d49e3d7bb5e3b3e6126bc81d1c1e0d7119 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 14 Jul 2018 21:37:24 +0200 Subject: [PATCH 8/9] ARM64: dts: meson-gxl: add support for the S905W SoC and the P281 board S905W is a new SoC from the GXL series. It is a cost-reduced version of the S905X. The P281 development board from Amlogic uses the same layout as the P231 (S905D development board). Thus the new P281 board inherits meson-gx-p23x-q20x.dtsi to avoid code-duplication. Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../boot/dts/amlogic/meson-gxl-s905w-p281.dts | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index 4dcffb0e3536..e55156dec237 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -18,6 +18,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts new file mode 100644 index 000000000000..6509c4950950 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-p281.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Martin Blumenstingl . + * Based on meson-gxl-s905d-p231.dts: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione + */ + +/dts-v1/; + +#include "meson-gxl-s905x.dtsi" +#include "meson-gx-p23x-q20x.dtsi" + +/ { + compatible = "amlogic,p281", "amlogic,s905w", "amlogic,meson-gxl"; + model = "Amlogic Meson GXL (S905W) P281 Development Board"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; + }; +}; From aaa080fa7e0f01f7cd8eb22a7385a4d8106c7478 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sat, 14 Jul 2018 21:37:25 +0200 Subject: [PATCH 9/9] ARM64: dts: meson-gxl: add support for the Oranth Tanix TX3 Mini The Tanix TX3 Mini is a TV box based on the Amlogic S905W chipset. There are two variants: - 1 GiB or 2 GiB of DDR3 memory - 8 GB or 16 GB eMMC flash Both variants come with: - 802.11 b/g/n wifi (Silicon Valley Microelectronics SSV6051, does not support Bluetooth) - an LED 7 segment display with an FD628 controller - HDMI and AV (CVBS) output - 2x USB (utilizing both USB ports provided by the SoC) - micro SD card slot - serial console (uart_AO) has to be soldered after opening the case The board seems to be very similar to the P23x and Q20x reference boards, which is why it includes meson-gx-p23x-q20x.dtsi: - eMMC reset routed to BOOT_9 - the SDIO wifi chip's reset line is routed to GPIOX_6 and the reference clock is 32.768KHz on PWM_E - SD card detection is routed to CARD_6 - vqmmc of all MMC controllers is hard-wired to 1.8V (VDDIO_BOOT) - uart_AO can be accessed after opening the case and soldering RX, TX and GND lines onto the exposed solder points (marked with RX, TX and GND) Signed-off-by: Martin Blumenstingl Reviewed-by: Neil Armstrong Signed-off-by: Kevin Hilman --- arch/arm64/boot/dts/amlogic/Makefile | 1 + .../dts/amlogic/meson-gxl-s905w-tx3-mini.dts | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+) create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile index e55156dec237..a97c0e2d7bc6 100644 --- a/arch/arm64/boot/dts/amlogic/Makefile +++ b/arch/arm64/boot/dts/amlogic/Makefile @@ -19,6 +19,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s805x-p241.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-p281.dtb +dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905w-tx3-mini.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-khadas-vim2.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb dtb-$(CONFIG_ARCH_MESON) += meson-gxm-q200.dtb diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts new file mode 100644 index 000000000000..789c819c99c4 --- /dev/null +++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905w-tx3-mini.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Martin Blumenstingl . + * Based on meson-gxl-s905d-p231.dts: + * - Copyright (c) 2016 Endless Computers, Inc. + * Author: Carlo Caione + */ + +/dts-v1/; + +#include "meson-gxl-s905x.dtsi" +#include "meson-gx-p23x-q20x.dtsi" + +/ { + compatible = "oranth,tx3-mini", "amlogic,s905w", "amlogic,meson-gxl"; + model = "Oranth Tanix TX3 Mini"; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x40000000>; /* 1 GiB or 2 GiB */ + }; +};