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ARM: p2v: move patching code to separate assembler source file
Move the phys2virt patching code into a separate .S file before doing some work on it. Suggested-by: Nicolas Pitre <nico@fluxnic.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
This commit is contained in:
Ard Biesheuvel
parent
22f2d23098
commit
eae78e1a97
3 changed files with 152 additions and 138 deletions
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@ -92,6 +92,7 @@ obj-$(CONFIG_PARAVIRT) += paravirt.o
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head-y := head$(MMUEXT).o
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obj-$(CONFIG_DEBUG_LL) += debug.o
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-$(CONFIG_ARM_PATCH_PHYS_VIRT) += phys2virt.o
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# This is executed very early using a temporary stack when no memory allocator
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# nor global data is available. Everything has to be allocated on the stack.
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@ -586,142 +586,4 @@ ENTRY(fixup_smp)
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ldmfd sp!, {r4 - r6, pc}
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ENDPROC(fixup_smp)
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#ifdef __ARMEB__
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#define LOW_OFFSET 0x4
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#define HIGH_OFFSET 0x0
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#else
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#define LOW_OFFSET 0x0
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#define HIGH_OFFSET 0x4
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#endif
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#ifdef CONFIG_ARM_PATCH_PHYS_VIRT
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/* __fixup_pv_table - patch the stub instructions with the delta between
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* PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
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* can be expressed by an immediate shifter operand. The stub instruction
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* has a form of '(add|sub) rd, rn, #imm'.
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*/
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__HEAD
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__fixup_pv_table:
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adr r0, 1f
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ldmia r0, {r3-r7}
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mvn ip, #0
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subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
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add r4, r4, r3 @ adjust table start address
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add r5, r5, r3 @ adjust table end address
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add r6, r6, r3 @ adjust __pv_phys_pfn_offset address
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add r7, r7, r3 @ adjust __pv_offset address
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mov r0, r8, lsr #PAGE_SHIFT @ convert to PFN
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str r0, [r6] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset
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strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits
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mov r6, r3, lsr #24 @ constant for add/sub instructions
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teq r3, r6, lsl #24 @ must be 16MiB aligned
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THUMB( it ne @ cross section branch )
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bne __error
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str r3, [r7, #LOW_OFFSET] @ save to __pv_offset low bits
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b __fixup_a_pv_table
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ENDPROC(__fixup_pv_table)
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.align
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1: .long .
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.long __pv_table_begin
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.long __pv_table_end
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2: .long __pv_phys_pfn_offset
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.long __pv_offset
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.text
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__fixup_a_pv_table:
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adr r0, 3f
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ldr r6, [r0]
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add r6, r6, r3
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ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word
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ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word
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mov r6, r6, lsr #24
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cmn r0, #1
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#ifdef CONFIG_THUMB2_KERNEL
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moveq r0, #0x200000 @ set bit 21, mov to mvn instruction
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lsls r6, #24
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beq 2f
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clz r7, r6
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lsr r6, #24
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lsl r6, r7
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bic r6, #0x0080
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lsrs r7, #1
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orrcs r6, #0x0080
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orr r6, r6, r7, lsl #12
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orr r6, #0x4000
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b 2f
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1: add r7, r3
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ldrh ip, [r7, #2]
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ARM_BE8(rev16 ip, ip)
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tst ip, #0x4000
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and ip, #0x8f00
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orrne ip, r6 @ mask in offset bits 31-24
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orreq ip, r0 @ mask in offset bits 7-0
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ARM_BE8(rev16 ip, ip)
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strh ip, [r7, #2]
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bne 2f
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ldrh ip, [r7]
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ARM_BE8(rev16 ip, ip)
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bic ip, #0x20
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orr ip, ip, r0, lsr #16
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ARM_BE8(rev16 ip, ip)
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strh ip, [r7]
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2: cmp r4, r5
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ldrcc r7, [r4], #4 @ use branch for delay slot
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bcc 1b
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bx lr
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#else
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moveq r0, #0x400000 @ set bit 22, mov to mvn instruction
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b 2f
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1: ldr ip, [r7, r3]
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#ifdef CONFIG_CPU_ENDIAN_BE8
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@ in BE8, we load data in BE, but instructions still in LE
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bic ip, ip, #0xff000000
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tst ip, #0x000f0000 @ check the rotation field
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orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24
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biceq ip, ip, #0x00004000 @ clear bit 22
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orreq ip, ip, r0, ror #8 @ mask in offset bits 7-0
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#else
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bic ip, ip, #0x000000ff
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tst ip, #0xf00 @ check the rotation field
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orrne ip, ip, r6 @ mask in offset bits 31-24
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biceq ip, ip, #0x400000 @ clear bit 22
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orreq ip, ip, r0 @ mask in offset bits 7-0
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#endif
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str ip, [r7, r3]
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2: cmp r4, r5
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ldrcc r7, [r4], #4 @ use branch for delay slot
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bcc 1b
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ret lr
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#endif
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ENDPROC(__fixup_a_pv_table)
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.align
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3: .long __pv_offset
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ENTRY(fixup_pv_table)
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stmfd sp!, {r4 - r7, lr}
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mov r3, #0 @ no offset
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mov r4, r0 @ r0 = table start
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add r5, r0, r1 @ r1 = table size
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bl __fixup_a_pv_table
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ldmfd sp!, {r4 - r7, pc}
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ENDPROC(fixup_pv_table)
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.data
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.align 2
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.globl __pv_phys_pfn_offset
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.type __pv_phys_pfn_offset, %object
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__pv_phys_pfn_offset:
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.word 0
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.size __pv_phys_pfn_offset, . -__pv_phys_pfn_offset
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.globl __pv_offset
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.type __pv_offset, %object
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__pv_offset:
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.quad 0
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.size __pv_offset, . -__pv_offset
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#endif
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#include "head-common.S"
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151
arch/arm/kernel/phys2virt.S
Normal file
151
arch/arm/kernel/phys2virt.S
Normal file
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@ -0,0 +1,151 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 1994-2002 Russell King
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* Copyright (c) 2003 ARM Limited
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* All Rights Reserved
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/page.h>
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#ifdef __ARMEB__
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#define LOW_OFFSET 0x4
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#define HIGH_OFFSET 0x0
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#else
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#define LOW_OFFSET 0x0
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#define HIGH_OFFSET 0x4
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#endif
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/*
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* __fixup_pv_table - patch the stub instructions with the delta between
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* PHYS_OFFSET and PAGE_OFFSET, which is assumed to be
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* 16MiB aligned.
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*
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* Called from head.S, which expects the following registers to be preserved:
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* r1 = machine no, r2 = atags or dtb,
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* r8 = phys_offset, r9 = cpuid, r10 = procinfo
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*/
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__HEAD
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ENTRY(__fixup_pv_table)
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adr r0, 1f
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ldmia r0, {r3-r7}
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mvn ip, #0
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subs r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
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add r4, r4, r3 @ adjust table start address
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add r5, r5, r3 @ adjust table end address
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add r6, r6, r3 @ adjust __pv_phys_pfn_offset address
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add r7, r7, r3 @ adjust __pv_offset address
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mov r0, r8, lsr #PAGE_SHIFT @ convert to PFN
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str r0, [r6] @ save computed PHYS_OFFSET to __pv_phys_pfn_offset
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strcc ip, [r7, #HIGH_OFFSET] @ save to __pv_offset high bits
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mov r6, r3, lsr #24 @ constant for add/sub instructions
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teq r3, r6, lsl #24 @ must be 16MiB aligned
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bne 0f
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str r3, [r7, #LOW_OFFSET] @ save to __pv_offset low bits
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b __fixup_a_pv_table
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0: mov r0, r0 @ deadloop on error
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b 0b
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ENDPROC(__fixup_pv_table)
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.align
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1: .long .
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.long __pv_table_begin
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.long __pv_table_end
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2: .long __pv_phys_pfn_offset
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.long __pv_offset
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.text
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__fixup_a_pv_table:
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adr r0, 3f
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ldr r6, [r0]
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add r6, r6, r3
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ldr r0, [r6, #HIGH_OFFSET] @ pv_offset high word
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ldr r6, [r6, #LOW_OFFSET] @ pv_offset low word
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mov r6, r6, lsr #24
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cmn r0, #1
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#ifdef CONFIG_THUMB2_KERNEL
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moveq r0, #0x200000 @ set bit 21, mov to mvn instruction
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lsls r6, #24
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beq 2f
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clz r7, r6
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lsr r6, #24
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lsl r6, r7
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bic r6, #0x0080
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lsrs r7, #1
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orrcs r6, #0x0080
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orr r6, r6, r7, lsl #12
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orr r6, #0x4000
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b 2f
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1: add r7, r3
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ldrh ip, [r7, #2]
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ARM_BE8(rev16 ip, ip)
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tst ip, #0x4000
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and ip, #0x8f00
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orrne ip, r6 @ mask in offset bits 31-24
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orreq ip, r0 @ mask in offset bits 7-0
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ARM_BE8(rev16 ip, ip)
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strh ip, [r7, #2]
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bne 2f
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ldrh ip, [r7]
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ARM_BE8(rev16 ip, ip)
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bic ip, #0x20
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orr ip, ip, r0, lsr #16
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ARM_BE8(rev16 ip, ip)
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strh ip, [r7]
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2: cmp r4, r5
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ldrcc r7, [r4], #4 @ use branch for delay slot
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bcc 1b
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bx lr
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#else
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moveq r0, #0x400000 @ set bit 22, mov to mvn instruction
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b 2f
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1: ldr ip, [r7, r3]
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#ifdef CONFIG_CPU_ENDIAN_BE8
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@ in BE8, we load data in BE, but instructions still in LE
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bic ip, ip, #0xff000000
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tst ip, #0x000f0000 @ check the rotation field
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orrne ip, ip, r6, lsl #24 @ mask in offset bits 31-24
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biceq ip, ip, #0x00004000 @ clear bit 22
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orreq ip, ip, r0, ror #8 @ mask in offset bits 7-0
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#else
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bic ip, ip, #0x000000ff
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tst ip, #0xf00 @ check the rotation field
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orrne ip, ip, r6 @ mask in offset bits 31-24
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biceq ip, ip, #0x400000 @ clear bit 22
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orreq ip, ip, r0 @ mask in offset bits 7-0
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#endif
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str ip, [r7, r3]
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2: cmp r4, r5
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ldrcc r7, [r4], #4 @ use branch for delay slot
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bcc 1b
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ret lr
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#endif
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ENDPROC(__fixup_a_pv_table)
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.align
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3: .long __pv_offset
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ENTRY(fixup_pv_table)
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stmfd sp!, {r4 - r7, lr}
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mov r3, #0 @ no offset
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mov r4, r0 @ r0 = table start
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add r5, r0, r1 @ r1 = table size
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bl __fixup_a_pv_table
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ldmfd sp!, {r4 - r7, pc}
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ENDPROC(fixup_pv_table)
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.data
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.align 2
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.globl __pv_phys_pfn_offset
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.type __pv_phys_pfn_offset, %object
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__pv_phys_pfn_offset:
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.word 0
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.size __pv_phys_pfn_offset, . -__pv_phys_pfn_offset
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.globl __pv_offset
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.type __pv_offset, %object
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__pv_offset:
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.quad 0
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.size __pv_offset, . -__pv_offset
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