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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 19:00:25 +00:00
make RAM device optional
Having a RAM device does not make sense for chips like GK20A which have no dedicated video memory. The dummy RAM device that we used so far works as a temporary band-aid, but in the longer term it is desirable for the driver to be able to work without any kind of VRAM. This patch adds a few conditionals in places where a RAM device was assumed to be present and allows some more objects to be allocated from the TT domain, allowing Nouveau to handle GPUs for which pfb->ram == NULL. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
parent
c6a7b026a3
commit
eaecf0326f
7 changed files with 57 additions and 17 deletions
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@ -869,13 +869,20 @@ nouveau_display_dumb_create(struct drm_file *file_priv, struct drm_device *dev,
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struct drm_mode_create_dumb *args)
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{
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struct nouveau_bo *bo;
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uint32_t domain;
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int ret;
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args->pitch = roundup(args->width * (args->bpp / 8), 256);
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args->size = args->pitch * args->height;
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args->size = roundup(args->size, PAGE_SIZE);
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ret = nouveau_gem_new(dev, args->size, 0, NOUVEAU_GEM_DOMAIN_VRAM, 0, 0, &bo);
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/* Use VRAM if there is any ; otherwise fallback to system memory */
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if (nouveau_drm(dev)->device.info.ram_size != 0)
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domain = NOUVEAU_GEM_DOMAIN_VRAM;
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else
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domain = NOUVEAU_GEM_DOMAIN_GART;
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ret = nouveau_gem_new(dev, args->size, 0, domain, 0, 0, &bo);
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if (ret)
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return ret;
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@ -82,6 +82,9 @@ nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
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u32 size_nc = 0;
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int ret;
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if (drm->device.info.ram_size == 0)
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return -ENOMEM;
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if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
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size_nc = 1 << nvbo->page_shift;
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@ -215,6 +215,7 @@ nv84_fence_create(struct nouveau_drm *drm)
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{
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struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device);
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struct nv84_fence_priv *priv;
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u32 domain;
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int ret;
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priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
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@ -231,10 +232,17 @@ nv84_fence_create(struct nouveau_drm *drm)
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priv->base.context_base = fence_context_alloc(priv->base.contexts);
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priv->base.uevent = true;
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ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0,
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TTM_PL_FLAG_VRAM, 0, 0, NULL, NULL, &priv->bo);
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/* Use VRAM if there is any ; otherwise fallback to system memory */
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domain = drm->device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM :
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/*
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* fences created in sysmem must be non-cached or we
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* will lose CPU/GPU coherency!
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*/
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TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED;
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ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, domain, 0,
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0, NULL, NULL, &priv->bo);
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if (ret == 0) {
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ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM, false);
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ret = nouveau_bo_pin(priv->bo, domain, false);
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if (ret == 0) {
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ret = nouveau_bo_map(priv->bo);
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if (ret)
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@ -139,9 +139,13 @@ nvkm_devobj_info(struct nvkm_object *object, void *data, u32 size)
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args->v0.chipset = device->chipset;
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args->v0.revision = device->chiprev;
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if (pfb) args->v0.ram_size = args->v0.ram_user = pfb->ram->size;
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else args->v0.ram_size = args->v0.ram_user = 0;
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if (imem) args->v0.ram_user = args->v0.ram_user - imem->reserved;
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if (pfb && pfb->ram)
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args->v0.ram_size = args->v0.ram_user = pfb->ram->size;
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else
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args->v0.ram_size = args->v0.ram_user = 0;
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if (imem && args->v0.ram_size > 0)
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args->v0.ram_user = args->v0.ram_user - imem->reserved;
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return 0;
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}
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@ -184,7 +184,7 @@ nvkm_pstate_prog(struct nvkm_clk *clk, int pstatei)
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nv_debug(clk, "setting performance state %d\n", pstatei);
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clk->pstate = pstatei;
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if (pfb->ram->calc) {
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if (pfb->ram && pfb->ram->calc) {
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int khz = pstate->base.domain[nv_clk_src_mem];
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do {
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ret = pfb->ram->calc(pfb, khz);
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@ -55,9 +55,11 @@ _nvkm_fb_fini(struct nvkm_object *object, bool suspend)
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struct nvkm_fb *pfb = (void *)object;
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int ret;
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ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend);
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if (ret && suspend)
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return ret;
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if (pfb->ram) {
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ret = nv_ofuncs(pfb->ram)->fini(nv_object(pfb->ram), suspend);
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if (ret && suspend)
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return ret;
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}
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return nvkm_subdev_fini(&pfb->base, suspend);
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}
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@ -72,9 +74,11 @@ _nvkm_fb_init(struct nvkm_object *object)
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if (ret)
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return ret;
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ret = nv_ofuncs(pfb->ram)->init(nv_object(pfb->ram));
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if (ret)
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return ret;
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if (pfb->ram) {
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ret = nv_ofuncs(pfb->ram)->init(nv_object(pfb->ram));
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if (ret)
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return ret;
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}
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for (i = 0; i < pfb->tile.regions; i++)
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pfb->tile.prog(pfb, i, &pfb->tile.region[i]);
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@ -91,9 +95,12 @@ _nvkm_fb_dtor(struct nvkm_object *object)
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for (i = 0; i < pfb->tile.regions; i++)
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pfb->tile.fini(pfb, i, &pfb->tile.region[i]);
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nvkm_mm_fini(&pfb->tags);
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nvkm_mm_fini(&pfb->vram);
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nvkm_object_ref(NULL, (struct nvkm_object **)&pfb->ram);
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if (pfb->ram) {
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nvkm_mm_fini(&pfb->vram);
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nvkm_object_ref(NULL, (struct nvkm_object **)&pfb->ram);
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}
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nvkm_subdev_destroy(&pfb->base);
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}
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@ -127,6 +134,9 @@ nvkm_fb_create_(struct nvkm_object *parent, struct nvkm_object *engine,
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pfb->memtype_valid = impl->memtype;
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if (!impl->ram)
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return 0;
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ret = nvkm_object_ctor(nv_object(pfb), NULL, impl->ram, NULL, 0, &ram);
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if (ret) {
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nv_fatal(pfb, "error detecting memory configuration!!\n");
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@ -136,7 +136,8 @@ gf100_ltc_dtor(struct nvkm_object *object)
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struct nvkm_ltc_priv *priv = (void *)object;
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nvkm_mm_fini(&priv->tags);
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nvkm_mm_free(&pfb->vram, &priv->tag_ram);
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if (pfb->ram)
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nvkm_mm_free(&pfb->vram, &priv->tag_ram);
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nvkm_ltc_destroy(priv);
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}
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@ -149,6 +150,12 @@ gf100_ltc_init_tag_ram(struct nvkm_fb *pfb, struct nvkm_ltc_priv *priv)
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u32 tag_size, tag_margin, tag_align;
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int ret;
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/* No VRAM, no tags for now. */
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if (!pfb->ram) {
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priv->num_tags = 0;
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goto mm_init;
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}
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/* tags for 1/4 of VRAM should be enough (8192/4 per GiB of VRAM) */
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priv->num_tags = (pfb->ram->size >> 17) / 4;
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if (priv->num_tags > (1 << 17))
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@ -183,6 +190,7 @@ gf100_ltc_init_tag_ram(struct nvkm_fb *pfb, struct nvkm_ltc_priv *priv)
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priv->tag_base = tag_base;
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}
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mm_init:
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ret = nvkm_mm_init(&priv->tags, 0, priv->num_tags, 1);
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return ret;
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}
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