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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf fixes from Ingo Molnar: "Misc kernel side fixes. Generic: - cgroup events counting fix x86: - Intel PMU truncated-parameter fix - RDPMC fix - API naming fix/rename - uncore driver big-hardware PCI enumeration fix - uncore driver filter constraint fix" * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/cgroup: Fix child event counting bug perf/x86/intel/uncore: Fix multi-domain PCI CHA enumeration bug on Skylake servers perf/x86/intel: Rename confusing 'freerunning PEBS' API and implementation to 'large PEBS' perf/x86/intel/uncore: Add missing filter constraint for SKX CHA event perf/x86/intel: Don't accidentally clear high bits in bdw_limit_period() perf/x86/intel: Disable userspace RDPMC usage for large PEBS
This commit is contained in:
commit
eaf67993f5
6 changed files with 49 additions and 33 deletions
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@ -2118,7 +2118,8 @@ static int x86_pmu_event_init(struct perf_event *event)
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event->destroy(event);
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}
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if (READ_ONCE(x86_pmu.attr_rdpmc))
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if (READ_ONCE(x86_pmu.attr_rdpmc) &&
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!(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
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event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED;
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return err;
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@ -2952,9 +2952,9 @@ static void intel_pebs_aliases_skl(struct perf_event *event)
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return intel_pebs_aliases_precdist(event);
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}
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static unsigned long intel_pmu_free_running_flags(struct perf_event *event)
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static unsigned long intel_pmu_large_pebs_flags(struct perf_event *event)
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{
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unsigned long flags = x86_pmu.free_running_flags;
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unsigned long flags = x86_pmu.large_pebs_flags;
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if (event->attr.use_clockid)
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flags &= ~PERF_SAMPLE_TIME;
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@ -2976,8 +2976,8 @@ static int intel_pmu_hw_config(struct perf_event *event)
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if (!event->attr.freq) {
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event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
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if (!(event->attr.sample_type &
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~intel_pmu_free_running_flags(event)))
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event->hw.flags |= PERF_X86_EVENT_FREERUNNING;
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~intel_pmu_large_pebs_flags(event)))
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event->hw.flags |= PERF_X86_EVENT_LARGE_PEBS;
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}
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if (x86_pmu.pebs_aliases)
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x86_pmu.pebs_aliases(event);
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@ -3194,7 +3194,7 @@ static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
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X86_CONFIG(.event=0xc0, .umask=0x01)) {
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if (left < 128)
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left = 128;
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left &= ~0x3fu;
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left &= ~0x3fULL;
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}
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return left;
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}
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@ -3460,7 +3460,7 @@ static __initconst const struct x86_pmu core_pmu = {
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.event_map = intel_pmu_event_map,
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.max_events = ARRAY_SIZE(intel_perfmon_event_map),
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.apic = 1,
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.free_running_flags = PEBS_FREERUNNING_FLAGS,
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.large_pebs_flags = LARGE_PEBS_FLAGS,
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/*
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* Intel PMCs cannot be accessed sanely above 32-bit width,
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@ -3502,7 +3502,7 @@ static __initconst const struct x86_pmu intel_pmu = {
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.event_map = intel_pmu_event_map,
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.max_events = ARRAY_SIZE(intel_perfmon_event_map),
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.apic = 1,
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.free_running_flags = PEBS_FREERUNNING_FLAGS,
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.large_pebs_flags = LARGE_PEBS_FLAGS,
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/*
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* Intel PMCs cannot be accessed sanely above 32 bit width,
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* so we install an artificial 1<<31 period regardless of
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@ -935,7 +935,7 @@ void intel_pmu_pebs_add(struct perf_event *event)
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bool needed_cb = pebs_needs_sched_cb(cpuc);
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cpuc->n_pebs++;
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if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
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if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
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cpuc->n_large_pebs++;
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pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
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@ -975,7 +975,7 @@ void intel_pmu_pebs_del(struct perf_event *event)
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bool needed_cb = pebs_needs_sched_cb(cpuc);
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cpuc->n_pebs--;
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if (hwc->flags & PERF_X86_EVENT_FREERUNNING)
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if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
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cpuc->n_large_pebs--;
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pebs_update_state(needed_cb, cpuc, event->ctx->pmu);
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@ -1530,7 +1530,7 @@ void __init intel_ds_init(void)
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x86_pmu.pebs_record_size =
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sizeof(struct pebs_record_skl);
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x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
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x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;
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x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
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break;
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default:
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@ -3343,6 +3343,7 @@ static struct extra_reg skx_uncore_cha_extra_regs[] = {
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SNBEP_CBO_EVENT_EXTRA_REG(0x9134, 0xffff, 0x4),
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SNBEP_CBO_EVENT_EXTRA_REG(0x35, 0xff, 0x8),
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SNBEP_CBO_EVENT_EXTRA_REG(0x36, 0xff, 0x8),
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SNBEP_CBO_EVENT_EXTRA_REG(0x38, 0xff, 0x3),
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EVENT_EXTRA_END
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};
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@ -3562,24 +3563,27 @@ static struct intel_uncore_type *skx_msr_uncores[] = {
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NULL,
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};
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/*
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* To determine the number of CHAs, it should read bits 27:0 in the CAPID6
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* register which located at Device 30, Function 3, Offset 0x9C. PCI ID 0x2083.
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*/
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#define SKX_CAPID6 0x9c
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#define SKX_CHA_BIT_MASK GENMASK(27, 0)
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static int skx_count_chabox(void)
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{
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struct pci_dev *chabox_dev = NULL;
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int bus, count = 0;
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struct pci_dev *dev = NULL;
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u32 val = 0;
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while (1) {
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chabox_dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x208d, chabox_dev);
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if (!chabox_dev)
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break;
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if (count == 0)
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bus = chabox_dev->bus->number;
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if (bus != chabox_dev->bus->number)
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break;
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count++;
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}
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dev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x2083, dev);
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if (!dev)
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goto out;
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pci_dev_put(chabox_dev);
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return count;
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pci_read_config_dword(dev, SKX_CAPID6, &val);
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val &= SKX_CHA_BIT_MASK;
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out:
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pci_dev_put(dev);
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return hweight32(val);
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}
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void skx_uncore_cpu_init(void)
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@ -69,7 +69,7 @@ struct event_constraint {
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#define PERF_X86_EVENT_RDPMC_ALLOWED 0x0100 /* grant rdpmc permission */
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#define PERF_X86_EVENT_EXCL_ACCT 0x0200 /* accounted EXCL event */
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#define PERF_X86_EVENT_AUTO_RELOAD 0x0400 /* use PEBS auto-reload */
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#define PERF_X86_EVENT_FREERUNNING 0x0800 /* use freerunning PEBS */
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#define PERF_X86_EVENT_LARGE_PEBS 0x0800 /* use large PEBS */
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struct amd_nb {
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@ -88,7 +88,7 @@ struct amd_nb {
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* REGS_USER can be handled for events limited to ring 3.
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*
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*/
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#define PEBS_FREERUNNING_FLAGS \
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#define LARGE_PEBS_FLAGS \
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(PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
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PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
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PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
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@ -608,7 +608,7 @@ struct x86_pmu {
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struct event_constraint *pebs_constraints;
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void (*pebs_aliases)(struct perf_event *event);
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int max_pebs_events;
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unsigned long free_running_flags;
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unsigned long large_pebs_flags;
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/*
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* Intel LBR
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@ -724,9 +724,15 @@ static inline void __update_cgrp_time(struct perf_cgroup *cgrp)
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static inline void update_cgrp_time_from_cpuctx(struct perf_cpu_context *cpuctx)
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{
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struct perf_cgroup *cgrp_out = cpuctx->cgrp;
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if (cgrp_out)
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__update_cgrp_time(cgrp_out);
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struct perf_cgroup *cgrp = cpuctx->cgrp;
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struct cgroup_subsys_state *css;
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if (cgrp) {
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for (css = &cgrp->css; css; css = css->parent) {
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cgrp = container_of(css, struct perf_cgroup, css);
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__update_cgrp_time(cgrp);
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}
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}
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}
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static inline void update_cgrp_time_from_event(struct perf_event *event)
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@ -754,6 +760,7 @@ perf_cgroup_set_timestamp(struct task_struct *task,
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{
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struct perf_cgroup *cgrp;
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struct perf_cgroup_info *info;
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struct cgroup_subsys_state *css;
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/*
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* ctx->lock held by caller
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return;
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cgrp = perf_cgroup_from_task(task, ctx);
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info = this_cpu_ptr(cgrp->info);
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info->timestamp = ctx->timestamp;
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for (css = &cgrp->css; css; css = css->parent) {
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cgrp = container_of(css, struct perf_cgroup, css);
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info = this_cpu_ptr(cgrp->info);
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info->timestamp = ctx->timestamp;
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}
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}
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static DEFINE_PER_CPU(struct list_head, cgrp_cpuctx_list);
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