mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-07 17:19:02 +00:00
These patches provide ability to add non-PSC
clocks to DaVinci clock framwork and are required to support USB PHY clock setting from USB PHY driver. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) iQIcBAABAgAGBQJXIzJyAAoJEGFBu2jqvgRNGywQAJaq3OHDj1ANi2ywu2LRqFCT jwxDAMm5FOBueQWLyA0ZT9oKF6a0ZAAvaRPFioozx/eIHLBa2AAKUpbfbZ6DB3Hd bF04LbCV6tkKTtGF3bOyHr/Sb+61xxJMoYpZnvqz8PlpzMqtntIKfBWqNqd/R+lz XE7WiTHgN8nrgQLkrT3pcr3AXhygnsu6p5CyC6pqwhmfQfZLFVjgIZiwqmmTd614 HYCwiBkYQvOp6+CTlbPXWLoekunu/87KBnQa8mHiOnDz4SzM3tokSvSvDxsxOkHj 1cVYJIqP6GbxIQavqRY3BLHXnCnV+On2pkGT1H7xhnosQM5EldfJ1zRibDV75BeI ynNYoLzStu9W7K07XoZrPHOK4cp3qvWDpYhlBVuDYFN9o5qBGq75NYDmSU2fBS64 3FaSdVEHtPlCnTSm699xoga91cwlfNqSs9gRhUzEokszrFxDONDSNgAiYs5UcI4k 9YC0gEFC6/j7dBM4YSOLtoHsF8J//Gyx47sH4zD/0YwK20zt3GL6cZ/KOXe1Ielu 6pxR0Zz3CEIlBTq59QxdSJ9lTcPMasfqJISFQyffLMLlU67gW6+b2NvGoXSIYC/u egGsgzhFp/g0VkineTy5K2PhAQ7c8cur/DgNyJX7ftvVxw14m/TMyrPxNNrGUVem 59zpwKenUpueloJqeion =3dg+ -----END PGP SIGNATURE----- Merge tag 'davinci-for-v4.7/soc-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc Merge "DaVinci SoC updates for v4.7 (part 2)" from Sekhar Nori: These patches provide ability to add non-PSC clocks to DaVinci clock framwork and are required to support USB PHY clock setting from USB PHY driver. * tag 'davinci-for-v4.7/soc-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: davinci: da850: use clk->set_parent for async3 ARM: davinci: Move clock init after ioremap.
This commit is contained in:
commit
eb07e08d54
8 changed files with 42 additions and 55 deletions
|
@ -577,7 +577,7 @@ EXPORT_SYMBOL(davinci_set_pllrate);
|
||||||
* than that used by default in <soc>.c file. The reference clock rate
|
* than that used by default in <soc>.c file. The reference clock rate
|
||||||
* should be updated early in the boot process; ideally soon after the
|
* should be updated early in the boot process; ideally soon after the
|
||||||
* clock tree has been initialized once with the default reference clock
|
* clock tree has been initialized once with the default reference clock
|
||||||
* rate (davinci_common_init()).
|
* rate (davinci_clk_init()).
|
||||||
*
|
*
|
||||||
* Returns 0 on success, error otherwise.
|
* Returns 0 on success, error otherwise.
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -103,12 +103,6 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
|
||||||
if (ret < 0)
|
if (ret < 0)
|
||||||
goto err;
|
goto err;
|
||||||
|
|
||||||
if (davinci_soc_info.cpu_clks) {
|
|
||||||
ret = davinci_clk_init(davinci_soc_info.cpu_clks);
|
|
||||||
|
|
||||||
if (ret != 0)
|
|
||||||
goto err;
|
|
||||||
}
|
|
||||||
|
|
||||||
return;
|
return;
|
||||||
|
|
||||||
|
|
|
@ -1214,4 +1214,6 @@ void __init da830_init(void)
|
||||||
|
|
||||||
da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
|
da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
|
||||||
WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
|
WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
|
||||||
|
|
||||||
|
davinci_clk_init(davinci_soc_info_da830.cpu_clks);
|
||||||
}
|
}
|
||||||
|
|
|
@ -34,9 +34,6 @@
|
||||||
#include "clock.h"
|
#include "clock.h"
|
||||||
#include "mux.h"
|
#include "mux.h"
|
||||||
|
|
||||||
/* SoC specific clock flags */
|
|
||||||
#define DA850_CLK_ASYNC3 BIT(16)
|
|
||||||
|
|
||||||
#define DA850_PLL1_BASE 0x01e1a000
|
#define DA850_PLL1_BASE 0x01e1a000
|
||||||
#define DA850_TIMER64P2_BASE 0x01f0c000
|
#define DA850_TIMER64P2_BASE 0x01f0c000
|
||||||
#define DA850_TIMER64P3_BASE 0x01f0d000
|
#define DA850_TIMER64P3_BASE 0x01f0d000
|
||||||
|
@ -161,6 +158,32 @@ static struct clk pll1_sysclk3 = {
|
||||||
.div_reg = PLLDIV3,
|
.div_reg = PLLDIV3,
|
||||||
};
|
};
|
||||||
|
|
||||||
|
static int da850_async3_set_parent(struct clk *clk, struct clk *parent)
|
||||||
|
{
|
||||||
|
u32 val;
|
||||||
|
|
||||||
|
val = readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
|
||||||
|
|
||||||
|
if (parent == &pll0_sysclk2) {
|
||||||
|
val &= ~CFGCHIP3_ASYNC3_CLKSRC;
|
||||||
|
} else if (parent == &pll1_sysclk2) {
|
||||||
|
val |= CFGCHIP3_ASYNC3_CLKSRC;
|
||||||
|
} else {
|
||||||
|
pr_err("Bad parent on async3 clock mux\n");
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
writel(val, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct clk async3_clk = {
|
||||||
|
.name = "async3",
|
||||||
|
.parent = &pll1_sysclk2,
|
||||||
|
.set_parent = da850_async3_set_parent,
|
||||||
|
};
|
||||||
|
|
||||||
static struct clk i2c0_clk = {
|
static struct clk i2c0_clk = {
|
||||||
.name = "i2c0",
|
.name = "i2c0",
|
||||||
.parent = &pll0_aux_clk,
|
.parent = &pll0_aux_clk,
|
||||||
|
@ -234,18 +257,16 @@ static struct clk uart0_clk = {
|
||||||
|
|
||||||
static struct clk uart1_clk = {
|
static struct clk uart1_clk = {
|
||||||
.name = "uart1",
|
.name = "uart1",
|
||||||
.parent = &pll0_sysclk2,
|
.parent = &async3_clk,
|
||||||
.lpsc = DA8XX_LPSC1_UART1,
|
.lpsc = DA8XX_LPSC1_UART1,
|
||||||
.gpsc = 1,
|
.gpsc = 1,
|
||||||
.flags = DA850_CLK_ASYNC3,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk uart2_clk = {
|
static struct clk uart2_clk = {
|
||||||
.name = "uart2",
|
.name = "uart2",
|
||||||
.parent = &pll0_sysclk2,
|
.parent = &async3_clk,
|
||||||
.lpsc = DA8XX_LPSC1_UART2,
|
.lpsc = DA8XX_LPSC1_UART2,
|
||||||
.gpsc = 1,
|
.gpsc = 1,
|
||||||
.flags = DA850_CLK_ASYNC3,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk aintc_clk = {
|
static struct clk aintc_clk = {
|
||||||
|
@ -300,10 +321,9 @@ static struct clk emac_clk = {
|
||||||
|
|
||||||
static struct clk mcasp_clk = {
|
static struct clk mcasp_clk = {
|
||||||
.name = "mcasp",
|
.name = "mcasp",
|
||||||
.parent = &pll0_sysclk2,
|
.parent = &async3_clk,
|
||||||
.lpsc = DA8XX_LPSC1_McASP0,
|
.lpsc = DA8XX_LPSC1_McASP0,
|
||||||
.gpsc = 1,
|
.gpsc = 1,
|
||||||
.flags = DA850_CLK_ASYNC3,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk lcdc_clk = {
|
static struct clk lcdc_clk = {
|
||||||
|
@ -355,10 +375,9 @@ static struct clk spi0_clk = {
|
||||||
|
|
||||||
static struct clk spi1_clk = {
|
static struct clk spi1_clk = {
|
||||||
.name = "spi1",
|
.name = "spi1",
|
||||||
.parent = &pll0_sysclk2,
|
.parent = &async3_clk,
|
||||||
.lpsc = DA8XX_LPSC1_SPI1,
|
.lpsc = DA8XX_LPSC1_SPI1,
|
||||||
.gpsc = 1,
|
.gpsc = 1,
|
||||||
.flags = DA850_CLK_ASYNC3,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk vpif_clk = {
|
static struct clk vpif_clk = {
|
||||||
|
@ -386,10 +405,9 @@ static struct clk dsp_clk = {
|
||||||
|
|
||||||
static struct clk ehrpwm_clk = {
|
static struct clk ehrpwm_clk = {
|
||||||
.name = "ehrpwm",
|
.name = "ehrpwm",
|
||||||
.parent = &pll0_sysclk2,
|
.parent = &async3_clk,
|
||||||
.lpsc = DA8XX_LPSC1_PWM,
|
.lpsc = DA8XX_LPSC1_PWM,
|
||||||
.gpsc = 1,
|
.gpsc = 1,
|
||||||
.flags = DA850_CLK_ASYNC3,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
#define DA8XX_EHRPWM_TBCLKSYNC BIT(12)
|
#define DA8XX_EHRPWM_TBCLKSYNC BIT(12)
|
||||||
|
@ -421,10 +439,9 @@ static struct clk ehrpwm_tbclk = {
|
||||||
|
|
||||||
static struct clk ecap_clk = {
|
static struct clk ecap_clk = {
|
||||||
.name = "ecap",
|
.name = "ecap",
|
||||||
.parent = &pll0_sysclk2,
|
.parent = &async3_clk,
|
||||||
.lpsc = DA8XX_LPSC1_ECAP,
|
.lpsc = DA8XX_LPSC1_ECAP,
|
||||||
.gpsc = 1,
|
.gpsc = 1,
|
||||||
.flags = DA850_CLK_ASYNC3,
|
|
||||||
};
|
};
|
||||||
|
|
||||||
static struct clk_lookup da850_clks[] = {
|
static struct clk_lookup da850_clks[] = {
|
||||||
|
@ -442,6 +459,7 @@ static struct clk_lookup da850_clks[] = {
|
||||||
CLK(NULL, "pll1_aux", &pll1_aux_clk),
|
CLK(NULL, "pll1_aux", &pll1_aux_clk),
|
||||||
CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
|
CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
|
||||||
CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
|
CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
|
||||||
|
CLK(NULL, "async3", &async3_clk),
|
||||||
CLK("i2c_davinci.1", NULL, &i2c0_clk),
|
CLK("i2c_davinci.1", NULL, &i2c0_clk),
|
||||||
CLK(NULL, "timer0", &timerp64_0_clk),
|
CLK(NULL, "timer0", &timerp64_0_clk),
|
||||||
CLK("davinci-wdt", NULL, &timerp64_1_clk),
|
CLK("davinci-wdt", NULL, &timerp64_1_clk),
|
||||||
|
@ -909,30 +927,6 @@ static struct davinci_timer_info da850_timer_info = {
|
||||||
.clocksource_id = T0_TOP,
|
.clocksource_id = T0_TOP,
|
||||||
};
|
};
|
||||||
|
|
||||||
static void da850_set_async3_src(int pllnum)
|
|
||||||
{
|
|
||||||
struct clk *clk, *newparent = pllnum ? &pll1_sysclk2 : &pll0_sysclk2;
|
|
||||||
struct clk_lookup *c;
|
|
||||||
unsigned int v;
|
|
||||||
int ret;
|
|
||||||
|
|
||||||
for (c = da850_clks; c->clk; c++) {
|
|
||||||
clk = c->clk;
|
|
||||||
if (clk->flags & DA850_CLK_ASYNC3) {
|
|
||||||
ret = clk_set_parent(clk, newparent);
|
|
||||||
WARN(ret, "DA850: unable to re-parent clock %s",
|
|
||||||
clk->name);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
|
|
||||||
if (pllnum)
|
|
||||||
v |= CFGCHIP3_ASYNC3_CLKSRC;
|
|
||||||
else
|
|
||||||
v &= ~CFGCHIP3_ASYNC3_CLKSRC;
|
|
||||||
__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_CPU_FREQ
|
#ifdef CONFIG_CPU_FREQ
|
||||||
/*
|
/*
|
||||||
* Notes:
|
* Notes:
|
||||||
|
@ -1328,15 +1322,6 @@ void __init da850_init(void)
|
||||||
if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
|
if (WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"))
|
||||||
return;
|
return;
|
||||||
|
|
||||||
/*
|
|
||||||
* Move the clock source of Async3 domain to PLL1 SYSCLK2.
|
|
||||||
* This helps keeping the peripherals on this domain insulated
|
|
||||||
* from CPU frequency changes caused by DVFS. The firmware sets
|
|
||||||
* both PLL0 and PLL1 to the same frequency so, there should not
|
|
||||||
* be any noticeable change even in non-DVFS use cases.
|
|
||||||
*/
|
|
||||||
da850_set_async3_src(1);
|
|
||||||
|
|
||||||
/* Unlock writing to PLL0 registers */
|
/* Unlock writing to PLL0 registers */
|
||||||
v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
|
v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP0_REG));
|
||||||
v &= ~CFGCHIP0_PLL_MASTER_LOCK;
|
v &= ~CFGCHIP0_PLL_MASTER_LOCK;
|
||||||
|
@ -1346,4 +1331,6 @@ void __init da850_init(void)
|
||||||
v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
|
v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
|
||||||
v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
|
v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
|
||||||
__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
|
__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
|
||||||
|
|
||||||
|
davinci_clk_init(davinci_soc_info_da850.cpu_clks);
|
||||||
}
|
}
|
||||||
|
|
|
@ -1052,6 +1052,7 @@ void __init dm355_init(void)
|
||||||
{
|
{
|
||||||
davinci_common_init(&davinci_soc_info_dm355);
|
davinci_common_init(&davinci_soc_info_dm355);
|
||||||
davinci_map_sysmod();
|
davinci_map_sysmod();
|
||||||
|
davinci_clk_init(davinci_soc_info_dm355.cpu_clks);
|
||||||
}
|
}
|
||||||
|
|
||||||
int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
|
int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
|
||||||
|
|
|
@ -1176,6 +1176,7 @@ void __init dm365_init(void)
|
||||||
{
|
{
|
||||||
davinci_common_init(&davinci_soc_info_dm365);
|
davinci_common_init(&davinci_soc_info_dm365);
|
||||||
davinci_map_sysmod();
|
davinci_map_sysmod();
|
||||||
|
davinci_clk_init(davinci_soc_info_dm365.cpu_clks);
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct resource dm365_vpss_resources[] = {
|
static struct resource dm365_vpss_resources[] = {
|
||||||
|
|
|
@ -932,6 +932,7 @@ void __init dm644x_init(void)
|
||||||
{
|
{
|
||||||
davinci_common_init(&davinci_soc_info_dm644x);
|
davinci_common_init(&davinci_soc_info_dm644x);
|
||||||
davinci_map_sysmod();
|
davinci_map_sysmod();
|
||||||
|
davinci_clk_init(davinci_soc_info_dm644x.cpu_clks);
|
||||||
}
|
}
|
||||||
|
|
||||||
int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
|
int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
|
||||||
|
|
|
@ -956,6 +956,7 @@ void __init dm646x_init(void)
|
||||||
{
|
{
|
||||||
davinci_common_init(&davinci_soc_info_dm646x);
|
davinci_common_init(&davinci_soc_info_dm646x);
|
||||||
davinci_map_sysmod();
|
davinci_map_sysmod();
|
||||||
|
davinci_clk_init(davinci_soc_info_dm646x.cpu_clks);
|
||||||
}
|
}
|
||||||
|
|
||||||
static int __init dm646x_init_devices(void)
|
static int __init dm646x_init_devices(void)
|
||||||
|
|
Loading…
Reference in a new issue