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MIPS: ingenic: Select CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER
The clock driving the XBurst CPUs in Ingenic SoCs is integer divided from the main PLL. As such, it is possible to control the frequency of the CPU, either by changing the divider, or by changing the rate of the main PLL. The XBurst CPUs also lack the CP0 timer; the TCU, a separate piece of hardware in the SoC, provides this functionality. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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@ -429,6 +429,8 @@ config MACH_INGENIC_SOC
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select MIPS_GENERIC
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select MACH_INGENIC
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select SYS_SUPPORTS_ZBOOT_UART16550
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select CPU_SUPPORTS_CPUFREQ
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select MIPS_EXTERNAL_TIMER
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config LANTIQ
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bool "Lantiq based platforms"
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