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drm/amd/pm: correct the requirement for umc cdr workaround
The workaround can be applied only with UCLK DPM enabled. And expand the workaround to more Navi10 SKUs and also Navi14. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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1 changed files with 9 additions and 10 deletions
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@ -2185,19 +2185,18 @@ static int navi10_run_btc(struct smu_context *smu)
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return ret;
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}
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static inline bool navi10_need_umc_cdr_12gbps_workaround(struct amdgpu_device *adev)
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static bool navi10_need_umc_cdr_12gbps_workaround(struct smu_context *smu)
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{
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if (adev->asic_type != CHIP_NAVI10)
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struct amdgpu_device *adev = smu->adev;
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if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
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return false;
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if (adev->pdev->device == 0x731f &&
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(adev->pdev->revision == 0xc2 ||
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adev->pdev->revision == 0xc3 ||
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adev->pdev->revision == 0xca ||
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adev->pdev->revision == 0xcb))
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if (adev->asic_type == CHIP_NAVI10 ||
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adev->asic_type == CHIP_NAVI14)
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return true;
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else
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return false;
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return false;
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}
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static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu)
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@ -2286,7 +2285,7 @@ static int navi10_disable_umc_cdr_12gbps_workaround(struct smu_context *smu)
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uint32_t param;
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int ret = 0;
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if (!navi10_need_umc_cdr_12gbps_workaround(adev))
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if (!navi10_need_umc_cdr_12gbps_workaround(smu))
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return 0;
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ret = smu_cmn_get_smc_version(smu, NULL, &pmfw_version);
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