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arm64: dts: renesas: r9a07g044: Add WDT nodes

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Add WDT{0, 1, 2} nodes to RZ/G2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20211123141420.23529-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das 2021-11-23 14:14:19 +00:00 committed by Geert Uytterhoeven
parent fee3eae133
commit eb7621ce33
1 changed files with 45 additions and 0 deletions
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45
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
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@ -792,6 +792,51 @@ hsusb: usb@11c60000 {
status = "disabled";
};
wdt0: watchdog@12800800 {
compatible = "renesas,r9a07g044-wdt",
"renesas,rzg2l-wdt";
reg = <0 0x12800800 0 0x400>;
clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
<&cpg CPG_MOD R9A07G044_WDT0_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G044_WDT0_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
wdt1: watchdog@12800c00 {
compatible = "renesas,r9a07g044-wdt",
"renesas,rzg2l-wdt";
reg = <0 0x12800C00 0 0x400>;
clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
<&cpg CPG_MOD R9A07G044_WDT1_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G044_WDT1_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
wdt2: watchdog@12800400 {
compatible = "renesas,r9a07g044-wdt",
"renesas,rzg2l-wdt";
reg = <0 0x12800400 0 0x400>;
clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>,
<&cpg CPG_MOD R9A07G044_WDT2_CLK>;
clock-names = "pclk", "oscclk";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "wdt", "perrout";
resets = <&cpg R9A07G044_WDT2_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
ostm0: timer@12801000 {
compatible = "renesas,r9a07g044-ostm",
"renesas,ostm";