ARM: dts: ixp4xx: Add Intel IXDP425 etc reference designs
The IXDP425, IXCDP1100, KIXRP435 and IXDP465 are similar Intel reference designs for IXP42x, IXP43x and IXP4[56]x. This adds device trees for these so the board files can be migrated. Cc: Deepak Saxena <dsaxena@plexity.net> Cc: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Linus Walleij
parent
16d8d49b56
commit
ec0384026c
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@ -242,6 +242,9 @@ dtb-$(CONFIG_ARCH_INTEGRATOR) += \
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dtb-$(CONFIG_ARCH_IXP4XX) += \
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intel-ixp42x-linksys-nslu2.dtb \
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intel-ixp42x-welltech-epbx100.dtb \
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intel-ixp42x-ixdp425.dtb \
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intel-ixp43x-kixrp435.dtb \
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intel-ixp46x-ixdp465.dtb \
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intel-ixp42x-iomega-nas100d.dtb \
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intel-ixp42x-dlink-dsm-g600.dtb \
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intel-ixp42x-gateworks-gw2348.dtb \
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@ -0,0 +1,72 @@
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// SPDX-License-Identifier: ISC
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/*
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* Device Tree file for the Intel IXDP425 also known as IXCDP1100 Control Plane
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* processor reference design.
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*
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* This platform has the codename "Richfield".
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*
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* This machine is based on a 533 MHz IXP425.
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*/
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/dts-v1/;
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#include "intel-ixp42x.dtsi"
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#include "intel-ixp4xx-reference-design.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "Intel IXDP425/IXCDP1100 Richfield Reference Design";
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compatible = "intel,ixdp425", "intel,ixp42x";
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#address-cells = <1>;
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#size-cells = <1>;
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soc {
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bus@c4000000 {
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flash@0,0 {
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compatible = "intel,ixp4xx-flash", "cfi-flash";
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bank-width = <2>;
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/* Enable writes on the expansion bus */
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intel,ixp4xx-eb-write-enable = <1>;
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/* 16 MB of Flash mapped in at CS0 */
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reg = <0 0x00000000 0x1000000>;
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partitions {
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compatible = "redboot-fis";
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/* Eraseblock at 0x0fe0000 */
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fis-index-block = <0x7f>;
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};
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};
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};
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/* EthB */
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ethernet@c8009000 {
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status = "ok";
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queue-rx = <&qmgr 3>;
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queue-txready = <&qmgr 20>;
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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/* EthC */
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ethernet@c800a000 {
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status = "ok";
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queue-rx = <&qmgr 4>;
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queue-txready = <&qmgr 21>;
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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};
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};
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};
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@ -0,0 +1,68 @@
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// SPDX-License-Identifier: ISC
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/*
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* Device Tree file for the Intel KIXRP435 Control Plane
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* processor reference design.
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*/
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/dts-v1/;
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#include "intel-ixp43x.dtsi"
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#include "intel-ixp4xx-reference-design.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "Intel KIXRP435 Reference Design";
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compatible = "intel,kixrp435", "intel,ixp43x";
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#address-cells = <1>;
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#size-cells = <1>;
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soc {
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bus@c4000000 {
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flash@0,0 {
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compatible = "intel,ixp4xx-flash", "cfi-flash";
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bank-width = <2>;
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/* Enable writes on the expansion bus */
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intel,ixp4xx-eb-write-enable = <1>;
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/* 16 MB of Flash mapped in at CS0 */
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reg = <0 0x00000000 0x1000000>;
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partitions {
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compatible = "redboot-fis";
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/* Eraseblock at 0x0fe0000 */
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fis-index-block = <0x7f>;
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};
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};
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};
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/* CHECKME: ethernet set-up taken from Gateworks Cambria */
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ethernet@c800a000 {
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status = "ok";
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queue-rx = <&qmgr 4>;
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queue-txready = <&qmgr 21>;
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phy-mode = "rgmii";
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phy-handle = <&phy1>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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};
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};
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};
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ethernet@c800c000 {
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status = "ok";
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queue-rx = <&qmgr 2>;
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queue-txready = <&qmgr 19>;
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phy-mode = "rgmii";
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phy-handle = <&phy2>;
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intel,npe-handle = <&npe 0>;
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};
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};
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};
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@ -0,0 +1,38 @@
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// SPDX-License-Identifier: ISC
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/*
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* Device Tree file for the Intel IXDP465 Control Plane processor reference
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* design, codename "BMP".
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*/
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/dts-v1/;
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#include "intel-ixp45x-ixp46x.dtsi"
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#include "intel-ixp4xx-reference-design.dtsi"
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#include <dt-bindings/input/input.h>
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/ {
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model = "Intel IXDP465 BMP Reference Design";
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compatible = "intel,ixdp465", "intel,ixp46x";
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#address-cells = <1>;
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#size-cells = <1>;
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soc {
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bus@c4000000 {
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flash@0,0 {
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compatible = "intel,ixp4xx-flash", "cfi-flash";
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bank-width = <2>;
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/* Enable writes on the expansion bus */
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intel,ixp4xx-eb-write-enable = <1>;
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/* 32 MB of Flash mapped in at CS0 and CS1 */
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reg = <0 0x00000000 0x2000000>;
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partitions {
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compatible = "redboot-fis";
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/* Eraseblock at 0x1fe0000 */
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fis-index-block = <0xff>;
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};
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};
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};
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/* TODO: configure ethernet etc */
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};
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};
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@ -0,0 +1,132 @@
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// SPDX-License-Identifier: ISC
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/*
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* Device Tree include file for Intel reference designs for the
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* XScale Network Processors in the IXP 4xx series. Common device
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* set-up for IXDP425, IXCDP1100, KIXRP435 and IXDP465.
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*/
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/ {
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memory@0 {
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/*
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* The board supports up to 256 MB of memory. Here we put in
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* 64 MB and this may be modified by the boot loader.
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*/
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device_type = "memory";
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reg = <0x00000000 0x4000000>;
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};
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chosen {
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bootargs = "console=ttyS0,115200n8";
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stdout-path = "uart0:115200n8";
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};
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aliases {
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serial0 = &uart0;
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};
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i2c {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio0 7 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio0 6 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>;
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#address-cells = <1>;
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#size-cells = <0>;
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eeprom@50 {
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/*
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* Philips PCF8582C-2T/03 512byte I2C EEPROM
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* should behave like an Atmel 24c04.
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*/
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compatible = "atmel,24c04";
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reg = <0x50>;
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pagesize = <16>;
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size = <512>;
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read-only;
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};
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};
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soc {
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bus@c4000000 {
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/* Flash memory defined per-variant */
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nand-controller@3,0 {
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/* Some designs have a NAND on CS3 enable it here if present */
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status = "disabled";
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/*
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* gen_nand needs to be extended and documented to get
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* command byte = 1 and address byte = 2 from the device
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* tree.
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*/
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compatible = "gen_nand";
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/* Expansion bus set-up */
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intel,ixp4xx-eb-t1 = <0>;
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intel,ixp4xx-eb-t2 = <0>;
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intel,ixp4xx-eb-t3 = <1>; // 1 cycle extra strobe phase
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intel,ixp4xx-eb-t4 = <0>;
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intel,ixp4xx-eb-t5 = <0>;
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intel,ixp4xx-eb-cycle-type = <0>; // Intel cycle type
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intel,ixp4xx-eb-byte-access-on-halfword = <0>;
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intel,ixp4xx-eb-mux-address-and-data = <0>;
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intel,ixp4xx-eb-ahb-split-transfers = <0>;
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intel,ixp4xx-eb-write-enable = <1>;
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intel,ixp4xx-eb-byte-access = <1>;
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/* 512 bytes memory window */
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reg = <3 0x00000000 0x200>;
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nand-on-flash-bbt;
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nand-ecc-mode = "soft_bch";
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nand-ecc-step-size = <512>;
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nand-ecc-strength = <4>;
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nce-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* NCE */
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label = "ixp400 NAND";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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fs@0 {
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label = "ixp400 NAND FS 0";
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reg = <0x0 0x800000>;
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};
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fs@800000 {
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label = "ixp400 NAND FS 1";
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reg = <0x800000 0x0>;
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};
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};
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};
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};
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pci@c0000000 {
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status = "ok";
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/*
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* Taken from IXDP425 PCI boardfile.
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* PCI slots on the BIXMB425BD base card.
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* We have up to 4 slots (IDSEL) with 4 swizzled IRQs.
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*/
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interrupt-map =
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/* IDSEL 1 */
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<0x0800 0 0 1 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 1 is irq 11 */
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<0x0800 0 0 2 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 1 is irq 10 */
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<0x0800 0 0 3 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 1 is irq 9 */
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<0x0800 0 0 4 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 1 is irq 8 */
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/* IDSEL 2 */
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<0x1000 0 0 1 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 2 is irq 10 */
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<0x1000 0 0 2 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 2 is irq 9 */
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<0x1000 0 0 3 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 2 is irq 8 */
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<0x1000 0 0 4 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 2 is irq 11 */
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/* IDSEL 3 */
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<0x1800 0 0 1 &gpio0 9 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 3 is irq 9 */
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<0x1800 0 0 2 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 3 is irq 8 */
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<0x1800 0 0 3 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 3 is irq 11 */
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<0x1800 0 0 4 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT D on slot 3 is irq 10 */
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/* IDSEL 4 */
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<0x2000 0 0 1 &gpio0 8 IRQ_TYPE_LEVEL_LOW>, /* INT A on slot 4 is irq 8 */
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<0x2000 0 0 2 &gpio0 11 IRQ_TYPE_LEVEL_LOW>, /* INT B on slot 4 is irq 11 */
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<0x2000 0 0 3 &gpio0 10 IRQ_TYPE_LEVEL_LOW>, /* INT C on slot 4 is irq 10 */
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<0x2000 0 0 4 &gpio0 9 IRQ_TYPE_LEVEL_LOW>; /* INT D on slot 4 is irq 9 */
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};
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};
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};
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