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drm/i915/tgl: Implement Wa_1409804808
This workaround the CS not done issue on PIPE_CONTROL. v2: - replaced BIT() by REG_BIT() in all GEN7_ROW_CHICKEN2() bits - shortened the name of the new bit BSpec: 52890 BSpec: 46218 Cc: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200227220101.321671-1-jose.souza@intel.com
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2 changed files with 9 additions and 2 deletions
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@ -1362,6 +1362,12 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
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GEN12_DISABLE_EARLY_READ);
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}
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if (IS_TIGERLAKE(i915)) {
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/* Wa_1409804808:tgl */
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wa_masked_en(wal, GEN7_ROW_CHICKEN2,
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GEN12_PUSH_CONST_DEREF_HOLD_DIS);
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}
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if (IS_GEN(i915, 11)) {
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/* This is not an Wa. Enable for better image quality */
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wa_masked_en(wal,
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@ -9140,8 +9140,9 @@ enum {
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#define THROTTLE_12_5 (7 << 2)
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#define DISABLE_EARLY_EOT (1 << 1)
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#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
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#define GEN12_DISABLE_EARLY_READ BIT(14)
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#define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4)
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#define GEN12_DISABLE_EARLY_READ REG_BIT(14)
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#define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8)
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#define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4)
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#define DOP_CLOCK_GATING_DISABLE (1 << 0)
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