dt-bindings: opp: Convert qcom-nvmem-cpufreq to DT schema
Convert qcom-nvmem-cpufreq to DT schema format, splitting it into an OPP schema and a CPUFreq schema in the process. Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
This commit is contained in:
Yassine Oudjana
Viresh Kumar
parent
784adeb3a3
commit
ec24d1d554
|
|
@ -0,0 +1,166 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/cpufreq/qcom-cpufreq-nvmem.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. NVMEM CPUFreq bindings
|
||||
|
||||
maintainers:
|
||||
- Ilia Lin <ilia.lin@kernel.org>
|
||||
|
||||
description: |
|
||||
In certain Qualcomm Technologies, Inc. SoCs such as QCS404, The CPU supply
|
||||
voltage is dynamically configured by Core Power Reduction (CPR) depending on
|
||||
current CPU frequency and efuse values.
|
||||
CPR provides a power domain with multiple levels that are selected depending
|
||||
on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level
|
||||
according to the required OPPs defined in the CPU OPP tables.
|
||||
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,qcs404
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
cpus:
|
||||
type: object
|
||||
|
||||
patternProperties:
|
||||
'cpu@[0-9a-f]+':
|
||||
type: object
|
||||
|
||||
properties:
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
power-domain-names:
|
||||
items:
|
||||
- const: cpr
|
||||
|
||||
required:
|
||||
- power-domains
|
||||
- power-domain-names
|
||||
|
||||
patternProperties:
|
||||
'^opp-table(-[a-z0-9]+)?$':
|
||||
if:
|
||||
properties:
|
||||
compatible:
|
||||
const: operating-points-v2-kryo-cpu
|
||||
then:
|
||||
patternProperties:
|
||||
'^opp-?[0-9]+$':
|
||||
required:
|
||||
- required-opps
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
examples:
|
||||
- |
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. QCS404";
|
||||
compatible = "qcom,qcs404";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
#cooling-cells = <2>;
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU1: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
#cooling-cells = <2>;
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU2: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x102>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
#cooling-cells = <2>;
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU3: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x103>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
#cooling-cells = <2>;
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
};
|
||||
|
||||
cpu_opp_table: opp-table-cpu {
|
||||
compatible = "operating-points-v2-kryo-cpu";
|
||||
opp-shared;
|
||||
|
||||
opp-1094400000 {
|
||||
opp-hz = /bits/ 64 <1094400000>;
|
||||
required-opps = <&cpr_opp1>;
|
||||
};
|
||||
opp-1248000000 {
|
||||
opp-hz = /bits/ 64 <1248000000>;
|
||||
required-opps = <&cpr_opp2>;
|
||||
};
|
||||
opp-1401600000 {
|
||||
opp-hz = /bits/ 64 <1401600000>;
|
||||
required-opps = <&cpr_opp3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpr_opp_table: opp-table-cpr {
|
||||
compatible = "operating-points-v2-qcom-level";
|
||||
|
||||
cpr_opp1: opp1 {
|
||||
opp-level = <1>;
|
||||
qcom,opp-fuse-level = <1>;
|
||||
};
|
||||
cpr_opp2: opp2 {
|
||||
opp-level = <2>;
|
||||
qcom,opp-fuse-level = <2>;
|
||||
};
|
||||
cpr_opp3: opp3 {
|
||||
opp-level = <3>;
|
||||
qcom,opp-fuse-level = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,257 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/opp/opp-v2-kryo-cpu.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Qualcomm Technologies, Inc. NVMEM OPP bindings
|
||||
|
||||
maintainers:
|
||||
- Ilia Lin <ilia.lin@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: opp-v2-base.yaml#
|
||||
|
||||
description: |
|
||||
In certain Qualcomm Technologies, Inc. SoCs like APQ8096 and MSM8996,
|
||||
the CPU frequencies subset and voltage value of each OPP varies based on
|
||||
the silicon variant in use.
|
||||
Qualcomm Technologies, Inc. Process Voltage Scaling Tables
|
||||
defines the voltage and frequency value based on the msm-id in SMEM
|
||||
and speedbin blown in the efuse combination.
|
||||
The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
|
||||
to provide the OPP framework with required information (existing HW bitmap).
|
||||
This is used to determine the voltage and frequency value for each OPP of
|
||||
operating-points-v2 table when it is parsed by the OPP framework.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: operating-points-v2-kryo-cpu
|
||||
|
||||
nvmem-cells:
|
||||
description: |
|
||||
A phandle pointing to a nvmem-cells node representing the
|
||||
efuse registers that has information about the
|
||||
speedbin that is used to select the right frequency/voltage
|
||||
value pair.
|
||||
|
||||
opp-shared: true
|
||||
|
||||
patternProperties:
|
||||
'^opp-?[0-9]+$':
|
||||
type: object
|
||||
|
||||
properties:
|
||||
opp-hz: true
|
||||
|
||||
opp-microvolt: true
|
||||
|
||||
opp-supported-hw:
|
||||
description: |
|
||||
A single 32 bit bitmap value, representing compatible HW.
|
||||
Bitmap:
|
||||
0: MSM8996 V3, speedbin 0
|
||||
1: MSM8996 V3, speedbin 1
|
||||
2: MSM8996 V3, speedbin 2
|
||||
3: unused
|
||||
4: MSM8996 SG, speedbin 0
|
||||
5: MSM8996 SG, speedbin 1
|
||||
6: MSM8996 SG, speedbin 2
|
||||
7-31: unused
|
||||
maximum: 0x77
|
||||
|
||||
clock-latency-ns: true
|
||||
|
||||
required-opps: true
|
||||
|
||||
required:
|
||||
- opp-hz
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
if:
|
||||
required:
|
||||
- nvmem-cells
|
||||
then:
|
||||
patternProperties:
|
||||
'^opp-?[0-9]+$':
|
||||
required:
|
||||
- opp-supported-hw
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
/ {
|
||||
model = "Qualcomm Technologies, Inc. DB820c";
|
||||
compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
clocks = <&kryocc 0>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
clocks = <&kryocc 0>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU2: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
clocks = <&kryocc 1>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_1>;
|
||||
L2_1: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU3: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "psci";
|
||||
cpu-idle-states = <&CPU_SLEEP_0>;
|
||||
capacity-dmips-mhz = <1024>;
|
||||
clocks = <&kryocc 1>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cluster0_opp: opp-table-0 {
|
||||
compatible = "operating-points-v2-kryo-cpu";
|
||||
nvmem-cells = <&speedbin_efuse>;
|
||||
opp-shared;
|
||||
|
||||
opp-307200000 {
|
||||
opp-hz = /bits/ 64 <307200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x77>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1593600000 {
|
||||
opp-hz = /bits/ 64 <1593600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x71>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2188800000 {
|
||||
opp-hz = /bits/ 64 <2188800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x10>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp-table-1 {
|
||||
compatible = "operating-points-v2-kryo-cpu";
|
||||
nvmem-cells = <&speedbin_efuse>;
|
||||
opp-shared;
|
||||
|
||||
opp-307200000 {
|
||||
opp-hz = /bits/ 64 <307200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x77>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1593600000 {
|
||||
opp-hz = /bits/ 64 <1593600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2150400000 {
|
||||
opp-hz = /bits/ 64 <2150400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x31>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2342400000 {
|
||||
opp-hz = /bits/ 64 <2342400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x10>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
};
|
||||
|
||||
smem {
|
||||
compatible = "qcom,smem";
|
||||
memory-region = <&smem_mem>;
|
||||
hwlocks = <&tcsr_mutex 3>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
qfprom: qfprom@74000 {
|
||||
compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
|
||||
reg = <0x00074000 0x8ff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
speedbin_efuse: speedbin@133 {
|
||||
reg = <0x133 0x1>;
|
||||
bits = <5 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,796 +0,0 @@
|
|||
Qualcomm Technologies, Inc. NVMEM CPUFreq and OPP bindings
|
||||
===================================
|
||||
|
||||
In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996,
|
||||
the CPU frequencies subset and voltage value of each OPP varies based on
|
||||
the silicon variant in use.
|
||||
Qualcomm Technologies, Inc. Process Voltage Scaling Tables
|
||||
defines the voltage and frequency value based on the msm-id in SMEM
|
||||
and speedbin blown in the efuse combination.
|
||||
The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
|
||||
to provide the OPP framework with required information (existing HW bitmap).
|
||||
This is used to determine the voltage and frequency value for each OPP of
|
||||
operating-points-v2 table when it is parsed by the OPP framework.
|
||||
|
||||
Required properties:
|
||||
--------------------
|
||||
In 'cpu' nodes:
|
||||
- operating-points-v2: Phandle to the operating-points-v2 table to use.
|
||||
|
||||
In 'operating-points-v2' table:
|
||||
- compatible: Should be
|
||||
- 'operating-points-v2-kryo-cpu' for apq8096, msm8996, msm8974,
|
||||
apq8064, ipq8064, msm8960 and ipq8074.
|
||||
|
||||
Optional properties:
|
||||
--------------------
|
||||
In 'cpu' nodes:
|
||||
- power-domains: A phandle pointing to the PM domain specifier which provides
|
||||
the performance states available for active state management.
|
||||
Please refer to the power-domains bindings
|
||||
Documentation/devicetree/bindings/power/power_domain.txt
|
||||
and also examples below.
|
||||
- power-domain-names: Should be
|
||||
- 'cpr' for qcs404.
|
||||
|
||||
In 'operating-points-v2' table:
|
||||
- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
|
||||
efuse registers that has information about the
|
||||
speedbin that is used to select the right frequency/voltage
|
||||
value pair.
|
||||
Please refer the for nvmem-cells
|
||||
bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
|
||||
and also examples below.
|
||||
|
||||
In every OPP node:
|
||||
- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
|
||||
Bitmap:
|
||||
0: MSM8996 V3, speedbin 0
|
||||
1: MSM8996 V3, speedbin 1
|
||||
2: MSM8996 V3, speedbin 2
|
||||
3: unused
|
||||
4: MSM8996 SG, speedbin 0
|
||||
5: MSM8996 SG, speedbin 1
|
||||
6: MSM8996 SG, speedbin 2
|
||||
7-31: unused
|
||||
|
||||
Example 1:
|
||||
---------
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
clocks = <&kryocc 0>;
|
||||
cpu-supply = <&pm8994_s11_saw>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
L2_0: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
clocks = <&kryocc 0>;
|
||||
cpu-supply = <&pm8994_s11_saw>;
|
||||
operating-points-v2 = <&cluster0_opp>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
CPU2: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x100>;
|
||||
enable-method = "psci";
|
||||
clocks = <&kryocc 1>;
|
||||
cpu-supply = <&pm8994_s11_saw>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_1>;
|
||||
L2_1: l2-cache {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
CPU3: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "qcom,kryo";
|
||||
reg = <0x0 0x101>;
|
||||
enable-method = "psci";
|
||||
clocks = <&kryocc 1>;
|
||||
cpu-supply = <&pm8994_s11_saw>;
|
||||
operating-points-v2 = <&cluster1_opp>;
|
||||
#cooling-cells = <2>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&CPU3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cluster0_opp: opp_table0 {
|
||||
compatible = "operating-points-v2-kryo-cpu";
|
||||
nvmem-cells = <&speedbin_efuse>;
|
||||
opp-shared;
|
||||
|
||||
opp-307200000 {
|
||||
opp-hz = /bits/ 64 <307200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x77>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-384000000 {
|
||||
opp-hz = /bits/ 64 <384000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-422400000 {
|
||||
opp-hz = /bits/ 64 <422400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-460800000 {
|
||||
opp-hz = /bits/ 64 <460800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-480000000 {
|
||||
opp-hz = /bits/ 64 <480000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-537600000 {
|
||||
opp-hz = /bits/ 64 <537600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-556800000 {
|
||||
opp-hz = /bits/ 64 <556800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-614400000 {
|
||||
opp-hz = /bits/ 64 <614400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-652800000 {
|
||||
opp-hz = /bits/ 64 <652800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-691200000 {
|
||||
opp-hz = /bits/ 64 <691200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-729600000 {
|
||||
opp-hz = /bits/ 64 <729600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-768000000 {
|
||||
opp-hz = /bits/ 64 <768000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-844800000 {
|
||||
opp-hz = /bits/ 64 <844800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x77>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-902400000 {
|
||||
opp-hz = /bits/ 64 <902400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-960000000 {
|
||||
opp-hz = /bits/ 64 <960000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-979200000 {
|
||||
opp-hz = /bits/ 64 <979200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1036800000 {
|
||||
opp-hz = /bits/ 64 <1036800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1056000000 {
|
||||
opp-hz = /bits/ 64 <1056000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1113600000 {
|
||||
opp-hz = /bits/ 64 <1113600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1132800000 {
|
||||
opp-hz = /bits/ 64 <1132800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1190400000 {
|
||||
opp-hz = /bits/ 64 <1190400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1209600000 {
|
||||
opp-hz = /bits/ 64 <1209600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1228800000 {
|
||||
opp-hz = /bits/ 64 <1228800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1286400000 {
|
||||
opp-hz = /bits/ 64 <1286400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1324800000 {
|
||||
opp-hz = /bits/ 64 <1324800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x5>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1363200000 {
|
||||
opp-hz = /bits/ 64 <1363200000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x72>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1401600000 {
|
||||
opp-hz = /bits/ 64 <1401600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x5>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1440000000 {
|
||||
opp-hz = /bits/ 64 <1440000000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1478400000 {
|
||||
opp-hz = /bits/ 64 <1478400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x1>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1497600000 {
|
||||
opp-hz = /bits/ 64 <1497600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x4>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1516800000 {
|
||||
opp-hz = /bits/ 64 <1516800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1593600000 {
|
||||
opp-hz = /bits/ 64 <1593600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x71>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1996800000 {
|
||||
opp-hz = /bits/ 64 <1996800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x20>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2188800000 {
|
||||
opp-hz = /bits/ 64 <2188800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x10>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1_opp: opp_table1 {
|
||||
compatible = "operating-points-v2-kryo-cpu";
|
||||
nvmem-cells = <&speedbin_efuse>;
|
||||
opp-shared;
|
||||
|
||||
opp-307200000 {
|
||||
opp-hz = /bits/ 64 <307200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x77>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-384000000 {
|
||||
opp-hz = /bits/ 64 <384000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-403200000 {
|
||||
opp-hz = /bits/ 64 <403200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-460800000 {
|
||||
opp-hz = /bits/ 64 <460800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-480000000 {
|
||||
opp-hz = /bits/ 64 <480000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-537600000 {
|
||||
opp-hz = /bits/ 64 <537600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-556800000 {
|
||||
opp-hz = /bits/ 64 <556800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-614400000 {
|
||||
opp-hz = /bits/ 64 <614400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-652800000 {
|
||||
opp-hz = /bits/ 64 <652800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-691200000 {
|
||||
opp-hz = /bits/ 64 <691200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-729600000 {
|
||||
opp-hz = /bits/ 64 <729600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-748800000 {
|
||||
opp-hz = /bits/ 64 <748800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-806400000 {
|
||||
opp-hz = /bits/ 64 <806400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-825600000 {
|
||||
opp-hz = /bits/ 64 <825600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-883200000 {
|
||||
opp-hz = /bits/ 64 <883200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-902400000 {
|
||||
opp-hz = /bits/ 64 <902400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-940800000 {
|
||||
opp-hz = /bits/ 64 <940800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-979200000 {
|
||||
opp-hz = /bits/ 64 <979200000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1036800000 {
|
||||
opp-hz = /bits/ 64 <1036800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1056000000 {
|
||||
opp-hz = /bits/ 64 <1056000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1113600000 {
|
||||
opp-hz = /bits/ 64 <1113600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1132800000 {
|
||||
opp-hz = /bits/ 64 <1132800000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1190400000 {
|
||||
opp-hz = /bits/ 64 <1190400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1209600000 {
|
||||
opp-hz = /bits/ 64 <1209600000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1248000000 {
|
||||
opp-hz = /bits/ 64 <1248000000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1286400000 {
|
||||
opp-hz = /bits/ 64 <1286400000>;
|
||||
opp-microvolt = <905000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1324800000 {
|
||||
opp-hz = /bits/ 64 <1324800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1363200000 {
|
||||
opp-hz = /bits/ 64 <1363200000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1401600000 {
|
||||
opp-hz = /bits/ 64 <1401600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1440000000 {
|
||||
opp-hz = /bits/ 64 <1440000000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1478400000 {
|
||||
opp-hz = /bits/ 64 <1478400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1516800000 {
|
||||
opp-hz = /bits/ 64 <1516800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1555200000 {
|
||||
opp-hz = /bits/ 64 <1555200000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1593600000 {
|
||||
opp-hz = /bits/ 64 <1593600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1632000000 {
|
||||
opp-hz = /bits/ 64 <1632000000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1670400000 {
|
||||
opp-hz = /bits/ 64 <1670400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1708800000 {
|
||||
opp-hz = /bits/ 64 <1708800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1747200000 {
|
||||
opp-hz = /bits/ 64 <1747200000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x70>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1785600000 {
|
||||
opp-hz = /bits/ 64 <1785600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x7>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1804800000 {
|
||||
opp-hz = /bits/ 64 <1804800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x6>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1824000000 {
|
||||
opp-hz = /bits/ 64 <1824000000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x71>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1900800000 {
|
||||
opp-hz = /bits/ 64 <1900800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x74>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1920000000 {
|
||||
opp-hz = /bits/ 64 <1920000000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x1>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1977600000 {
|
||||
opp-hz = /bits/ 64 <1977600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x30>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-1996800000 {
|
||||
opp-hz = /bits/ 64 <1996800000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x1>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2054400000 {
|
||||
opp-hz = /bits/ 64 <2054400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x30>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2073600000 {
|
||||
opp-hz = /bits/ 64 <2073600000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x1>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2150400000 {
|
||||
opp-hz = /bits/ 64 <2150400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x31>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2246400000 {
|
||||
opp-hz = /bits/ 64 <2246400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x10>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
opp-2342400000 {
|
||||
opp-hz = /bits/ 64 <2342400000>;
|
||||
opp-microvolt = <1140000 905000 1140000>;
|
||||
opp-supported-hw = <0x10>;
|
||||
clock-latency-ns = <200000>;
|
||||
};
|
||||
};
|
||||
|
||||
....
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
....
|
||||
smem_mem: smem-mem@86000000 {
|
||||
reg = <0x0 0x86000000 0x0 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
....
|
||||
};
|
||||
|
||||
smem {
|
||||
compatible = "qcom,smem";
|
||||
memory-region = <&smem_mem>;
|
||||
hwlocks = <&tcsr_mutex 3>;
|
||||
};
|
||||
|
||||
soc {
|
||||
....
|
||||
qfprom: qfprom@74000 {
|
||||
compatible = "qcom,qfprom";
|
||||
reg = <0x00074000 0x8ff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
....
|
||||
speedbin_efuse: speedbin@133 {
|
||||
reg = <0x133 0x1>;
|
||||
bits = <5 3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
Example 2:
|
||||
---------
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
CPU0: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x100>;
|
||||
....
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU1: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x101>;
|
||||
....
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU2: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x102>;
|
||||
....
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
|
||||
CPU3: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x103>;
|
||||
....
|
||||
clocks = <&apcs_glb>;
|
||||
operating-points-v2 = <&cpu_opp_table>;
|
||||
power-domains = <&cpr>;
|
||||
power-domain-names = "cpr";
|
||||
};
|
||||
};
|
||||
|
||||
cpu_opp_table: cpu-opp-table {
|
||||
compatible = "operating-points-v2-kryo-cpu";
|
||||
opp-shared;
|
||||
|
||||
opp-1094400000 {
|
||||
opp-hz = /bits/ 64 <1094400000>;
|
||||
required-opps = <&cpr_opp1>;
|
||||
};
|
||||
opp-1248000000 {
|
||||
opp-hz = /bits/ 64 <1248000000>;
|
||||
required-opps = <&cpr_opp2>;
|
||||
};
|
||||
opp-1401600000 {
|
||||
opp-hz = /bits/ 64 <1401600000>;
|
||||
required-opps = <&cpr_opp3>;
|
||||
};
|
||||
};
|
||||
|
||||
cpr_opp_table: cpr-opp-table {
|
||||
compatible = "operating-points-v2-qcom-level";
|
||||
|
||||
cpr_opp1: opp1 {
|
||||
opp-level = <1>;
|
||||
qcom,opp-fuse-level = <1>;
|
||||
};
|
||||
cpr_opp2: opp2 {
|
||||
opp-level = <2>;
|
||||
qcom,opp-fuse-level = <2>;
|
||||
};
|
||||
cpr_opp3: opp3 {
|
||||
opp-level = <3>;
|
||||
qcom,opp-fuse-level = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
....
|
||||
|
||||
soc {
|
||||
....
|
||||
cpr: power-controller@b018000 {
|
||||
compatible = "qcom,qcs404-cpr", "qcom,cpr";
|
||||
reg = <0x0b018000 0x1000>;
|
||||
....
|
||||
vdd-apc-supply = <&pms405_s3>;
|
||||
#power-domain-cells = <0>;
|
||||
operating-points-v2 = <&cpr_opp_table>;
|
||||
....
|
||||
};
|
||||
};
|
||||
|
|
@ -15940,7 +15940,8 @@ QUALCOMM CPUFREQ DRIVER MSM8996/APQ8096
|
|||
M: Ilia Lin <ilia.lin@kernel.org>
|
||||
L: linux-pm@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt
|
||||
F: Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml
|
||||
F: Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml
|
||||
F: drivers/cpufreq/qcom-cpufreq-nvmem.c
|
||||
|
||||
QUALCOMM CRYPTO DRIVERS
|
||||
|
|
|
|||
Loading…
Reference in New Issue