mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-28 21:33:52 +00:00
spi: bcm2835: Allow arbitrary number of slaves
Since commit 571e31fa60 ("spi: bcm2835: Cache CS register value for
->prepare_message()"), the number of slaves has been limited by a
compile-time constant. This was necessitated by statically-sized
arrays in the driver private data which contain per-slave register
values.
As suggested by Mark, move those register values to a per-slave
controller_state which is allocated on ->setup and freed on ->cleanup.
The limitation on the number of slaves is thus lifted.
Signed-off-by: Lukas Wunner <lukas@wunner.de>
Cc: Joe Burmeister <joe.burmeister@devtank.co.uk>
Cc: Phil Elwell <phil@raspberrypi.com>
Link: https://lore.kernel.org/r/a847c01f09400801e74e0630bf5a0197591554da.1622150204.git.lukas@wunner.de
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Lukas Wunner
Mark Brown
parent
1a435466b0
commit
ec679bda63
1 changed files with 119 additions and 85 deletions
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@ -68,7 +68,6 @@
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#define BCM2835_SPI_FIFO_SIZE 64
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#define BCM2835_SPI_FIFO_SIZE_3_4 48
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#define BCM2835_SPI_DMA_MIN_LENGTH 96
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#define BCM2835_SPI_NUM_CS 24 /* raise as necessary */
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#define BCM2835_SPI_MODE_BITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
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| SPI_NO_CS | SPI_3WIRE)
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@ -96,8 +95,6 @@ MODULE_PARM_DESC(polling_limit_us,
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* @rx_prologue: bytes received without DMA if first RX sglist entry's
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* length is not a multiple of 4 (to overcome hardware limitation)
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* @tx_spillover: whether @tx_prologue spills over to second TX sglist entry
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* @prepare_cs: precalculated CS register value for ->prepare_message()
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* (uses slave-specific clock polarity and phase settings)
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* @debugfs_dir: the debugfs directory - neede to remove debugfs when
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* unloading the module
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* @count_transfer_polling: count of how often polling mode is used
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@ -107,7 +104,7 @@ MODULE_PARM_DESC(polling_limit_us,
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* These are counted as well in @count_transfer_polling and
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* @count_transfer_irq
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* @count_transfer_dma: count how often dma mode is used
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* @chip_select: SPI slave currently selected
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* @slv: SPI slave currently selected
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* (used by bcm2835_spi_dma_tx_done() to write @clear_rx_cs)
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* @tx_dma_active: whether a TX DMA descriptor is in progress
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* @rx_dma_active: whether a RX DMA descriptor is in progress
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@ -115,11 +112,6 @@ MODULE_PARM_DESC(polling_limit_us,
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* @fill_tx_desc: preallocated TX DMA descriptor used for RX-only transfers
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* (cyclically copies from zero page to TX FIFO)
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* @fill_tx_addr: bus address of zero page
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* @clear_rx_desc: preallocated RX DMA descriptor used for TX-only transfers
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* (cyclically clears RX FIFO by writing @clear_rx_cs to CS register)
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* @clear_rx_addr: bus address of @clear_rx_cs
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* @clear_rx_cs: precalculated CS register value to clear RX FIFO
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* (uses slave-specific clock polarity and phase settings)
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*/
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struct bcm2835_spi {
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void __iomem *regs;
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@ -134,7 +126,6 @@ struct bcm2835_spi {
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int tx_prologue;
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int rx_prologue;
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unsigned int tx_spillover;
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u32 prepare_cs[BCM2835_SPI_NUM_CS];
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struct dentry *debugfs_dir;
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u64 count_transfer_polling;
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@ -142,14 +133,28 @@ struct bcm2835_spi {
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u64 count_transfer_irq_after_polling;
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u64 count_transfer_dma;
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u8 chip_select;
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struct bcm2835_spidev *slv;
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unsigned int tx_dma_active;
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unsigned int rx_dma_active;
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struct dma_async_tx_descriptor *fill_tx_desc;
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dma_addr_t fill_tx_addr;
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struct dma_async_tx_descriptor *clear_rx_desc[BCM2835_SPI_NUM_CS];
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};
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/**
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* struct bcm2835_spidev - BCM2835 SPI slave
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* @prepare_cs: precalculated CS register value for ->prepare_message()
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* (uses slave-specific clock polarity and phase settings)
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* @clear_rx_desc: preallocated RX DMA descriptor used for TX-only transfers
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* (cyclically clears RX FIFO by writing @clear_rx_cs to CS register)
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* @clear_rx_addr: bus address of @clear_rx_cs
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* @clear_rx_cs: precalculated CS register value to clear RX FIFO
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* (uses slave-specific clock polarity and phase settings)
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*/
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struct bcm2835_spidev {
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u32 prepare_cs;
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struct dma_async_tx_descriptor *clear_rx_desc;
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dma_addr_t clear_rx_addr;
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u32 clear_rx_cs[BCM2835_SPI_NUM_CS] ____cacheline_aligned;
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u32 clear_rx_cs ____cacheline_aligned;
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};
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#if defined(CONFIG_DEBUG_FS)
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@ -624,8 +629,7 @@ static void bcm2835_spi_dma_tx_done(void *data)
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/* busy-wait for TX FIFO to empty */
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while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE))
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bcm2835_wr(bs, BCM2835_SPI_CS,
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bs->clear_rx_cs[bs->chip_select]);
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bcm2835_wr(bs, BCM2835_SPI_CS, bs->slv->clear_rx_cs);
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bs->tx_dma_active = false;
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smp_wmb();
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@ -646,18 +650,18 @@ static void bcm2835_spi_dma_tx_done(void *data)
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/**
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* bcm2835_spi_prepare_sg() - prepare and submit DMA descriptor for sglist
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* @ctlr: SPI master controller
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* @spi: SPI slave
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* @tfr: SPI transfer
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* @bs: BCM2835 SPI controller
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* @slv: BCM2835 SPI slave
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* @is_tx: whether to submit DMA descriptor for TX or RX sglist
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*
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* Prepare and submit a DMA descriptor for the TX or RX sglist of @tfr.
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* Return 0 on success or a negative error number.
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*/
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static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr,
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struct spi_device *spi,
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struct spi_transfer *tfr,
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struct bcm2835_spi *bs,
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struct bcm2835_spidev *slv,
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bool is_tx)
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{
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struct dma_chan *chan;
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@ -697,7 +701,7 @@ static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr,
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} else if (!tfr->rx_buf) {
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desc->callback = bcm2835_spi_dma_tx_done;
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desc->callback_param = ctlr;
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bs->chip_select = spi->chip_select;
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bs->slv = slv;
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}
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/* submit it to DMA-engine */
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@ -709,8 +713,8 @@ static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr,
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/**
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* bcm2835_spi_transfer_one_dma() - perform SPI transfer using DMA engine
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* @ctlr: SPI master controller
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* @spi: SPI slave
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* @tfr: SPI transfer
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* @slv: BCM2835 SPI slave
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* @cs: CS register
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*
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* For *bidirectional* transfers (both tx_buf and rx_buf are non-%NULL), set up
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@ -754,8 +758,8 @@ static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr,
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* performed at the end of an RX-only transfer.
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*/
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static int bcm2835_spi_transfer_one_dma(struct spi_controller *ctlr,
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struct spi_device *spi,
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struct spi_transfer *tfr,
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struct bcm2835_spidev *slv,
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u32 cs)
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{
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struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
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@ -773,7 +777,7 @@ static int bcm2835_spi_transfer_one_dma(struct spi_controller *ctlr,
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/* setup tx-DMA */
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if (bs->tx_buf) {
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ret = bcm2835_spi_prepare_sg(ctlr, spi, tfr, bs, true);
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ret = bcm2835_spi_prepare_sg(ctlr, tfr, bs, slv, true);
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} else {
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cookie = dmaengine_submit(bs->fill_tx_desc);
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ret = dma_submit_error(cookie);
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@ -799,9 +803,9 @@ static int bcm2835_spi_transfer_one_dma(struct spi_controller *ctlr,
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* this saves 10us or more.
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*/
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if (bs->rx_buf) {
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ret = bcm2835_spi_prepare_sg(ctlr, spi, tfr, bs, false);
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ret = bcm2835_spi_prepare_sg(ctlr, tfr, bs, slv, false);
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} else {
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cookie = dmaengine_submit(bs->clear_rx_desc[spi->chip_select]);
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cookie = dmaengine_submit(slv->clear_rx_desc);
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ret = dma_submit_error(cookie);
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}
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if (ret) {
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@ -850,8 +854,6 @@ static bool bcm2835_spi_can_dma(struct spi_controller *ctlr,
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static void bcm2835_dma_release(struct spi_controller *ctlr,
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struct bcm2835_spi *bs)
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{
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int i;
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if (ctlr->dma_tx) {
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dmaengine_terminate_sync(ctlr->dma_tx);
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@ -870,17 +872,6 @@ static void bcm2835_dma_release(struct spi_controller *ctlr,
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if (ctlr->dma_rx) {
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dmaengine_terminate_sync(ctlr->dma_rx);
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for (i = 0; i < BCM2835_SPI_NUM_CS; i++)
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if (bs->clear_rx_desc[i])
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dmaengine_desc_free(bs->clear_rx_desc[i]);
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if (bs->clear_rx_addr)
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dma_unmap_single(ctlr->dma_rx->device->dev,
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bs->clear_rx_addr,
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sizeof(bs->clear_rx_cs),
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DMA_TO_DEVICE);
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dma_release_channel(ctlr->dma_rx);
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ctlr->dma_rx = NULL;
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}
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@ -892,7 +883,7 @@ static int bcm2835_dma_init(struct spi_controller *ctlr, struct device *dev,
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struct dma_slave_config slave_config;
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const __be32 *addr;
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dma_addr_t dma_reg_base;
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int ret, i;
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int ret;
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/* base address in dma-space */
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addr = of_get_address(ctlr->dev.of_node, 0, NULL, NULL);
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@ -972,35 +963,6 @@ static int bcm2835_dma_init(struct spi_controller *ctlr, struct device *dev,
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if (ret)
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goto err_config;
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bs->clear_rx_addr = dma_map_single(ctlr->dma_rx->device->dev,
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bs->clear_rx_cs,
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sizeof(bs->clear_rx_cs),
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DMA_TO_DEVICE);
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if (dma_mapping_error(ctlr->dma_rx->device->dev, bs->clear_rx_addr)) {
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dev_err(dev, "cannot map clear_rx_cs - not using DMA mode\n");
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bs->clear_rx_addr = 0;
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ret = -ENOMEM;
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goto err_release;
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}
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for (i = 0; i < BCM2835_SPI_NUM_CS; i++) {
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bs->clear_rx_desc[i] = dmaengine_prep_dma_cyclic(ctlr->dma_rx,
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bs->clear_rx_addr + i * sizeof(u32),
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sizeof(u32), 0,
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DMA_MEM_TO_DEV, 0);
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if (!bs->clear_rx_desc[i]) {
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dev_err(dev, "cannot prepare clear_rx_desc - not using DMA mode\n");
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ret = -ENOMEM;
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goto err_release;
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}
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ret = dmaengine_desc_set_reuse(bs->clear_rx_desc[i]);
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if (ret) {
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dev_err(dev, "cannot reuse clear_rx_desc - not using DMA mode\n");
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goto err_release;
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}
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}
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/* all went well, so set can_dma */
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ctlr->can_dma = bcm2835_spi_can_dma;
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@ -1082,9 +1044,10 @@ static int bcm2835_spi_transfer_one(struct spi_controller *ctlr,
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struct spi_transfer *tfr)
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{
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struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
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struct bcm2835_spidev *slv = spi_get_ctldata(spi);
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unsigned long spi_hz, clk_hz, cdiv;
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unsigned long hz_per_byte, byte_limit;
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u32 cs = bs->prepare_cs[spi->chip_select];
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u32 cs = slv->prepare_cs;
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/* set clock */
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spi_hz = tfr->speed_hz;
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@ -1133,7 +1096,7 @@ static int bcm2835_spi_transfer_one(struct spi_controller *ctlr,
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* this 1 idle clock cycle pattern but runs the spi clock without gaps
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*/
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if (ctlr->can_dma && bcm2835_spi_can_dma(ctlr, spi, tfr))
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return bcm2835_spi_transfer_one_dma(ctlr, spi, tfr, cs);
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return bcm2835_spi_transfer_one_dma(ctlr, tfr, slv, cs);
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/* run in interrupt-mode */
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return bcm2835_spi_transfer_one_irq(ctlr, spi, tfr, cs, true);
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@ -1144,6 +1107,7 @@ static int bcm2835_spi_prepare_message(struct spi_controller *ctlr,
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{
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struct spi_device *spi = msg->spi;
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struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
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struct bcm2835_spidev *slv = spi_get_ctldata(spi);
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int ret;
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if (ctlr->can_dma) {
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@ -1162,7 +1126,7 @@ static int bcm2835_spi_prepare_message(struct spi_controller *ctlr,
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* Set up clock polarity before spi_transfer_one_message() asserts
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* chip select to avoid a gratuitous clock signal edge.
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*/
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bcm2835_wr(bs, BCM2835_SPI_CS, bs->prepare_cs[spi->chip_select]);
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bcm2835_wr(bs, BCM2835_SPI_CS, slv->prepare_cs);
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return 0;
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}
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@ -1188,17 +1152,81 @@ static int chip_match_name(struct gpio_chip *chip, void *data)
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return !strcmp(chip->label, data);
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}
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static void bcm2835_spi_cleanup(struct spi_device *spi)
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{
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struct bcm2835_spidev *slv = spi_get_ctldata(spi);
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struct spi_controller *ctlr = spi->controller;
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if (slv->clear_rx_desc)
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dmaengine_desc_free(slv->clear_rx_desc);
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if (slv->clear_rx_addr)
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dma_unmap_single(ctlr->dma_rx->device->dev,
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slv->clear_rx_addr,
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sizeof(u32),
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DMA_TO_DEVICE);
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kfree(slv);
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}
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static int bcm2835_spi_setup_dma(struct spi_controller *ctlr,
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struct spi_device *spi,
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struct bcm2835_spi *bs,
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struct bcm2835_spidev *slv)
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{
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int ret;
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if (!ctlr->dma_rx)
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return 0;
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slv->clear_rx_addr = dma_map_single(ctlr->dma_rx->device->dev,
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&slv->clear_rx_cs,
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sizeof(u32),
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DMA_TO_DEVICE);
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if (dma_mapping_error(ctlr->dma_rx->device->dev, slv->clear_rx_addr)) {
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dev_err(&spi->dev, "cannot map clear_rx_cs\n");
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slv->clear_rx_addr = 0;
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return -ENOMEM;
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}
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slv->clear_rx_desc = dmaengine_prep_dma_cyclic(ctlr->dma_rx,
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slv->clear_rx_addr,
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sizeof(u32), 0,
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DMA_MEM_TO_DEV, 0);
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if (!slv->clear_rx_desc) {
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dev_err(&spi->dev, "cannot prepare clear_rx_desc\n");
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return -ENOMEM;
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}
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ret = dmaengine_desc_set_reuse(slv->clear_rx_desc);
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if (ret) {
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dev_err(&spi->dev, "cannot reuse clear_rx_desc\n");
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return ret;
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}
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return 0;
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}
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static int bcm2835_spi_setup(struct spi_device *spi)
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{
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struct spi_controller *ctlr = spi->controller;
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struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
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struct bcm2835_spidev *slv = spi_get_ctldata(spi);
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struct gpio_chip *chip;
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int ret;
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u32 cs;
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if (spi->chip_select >= BCM2835_SPI_NUM_CS) {
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dev_err(&spi->dev, "only %d chip-selects supported\n",
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BCM2835_SPI_NUM_CS - 1);
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return -EINVAL;
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if (!slv) {
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slv = kzalloc(ALIGN(sizeof(*slv), dma_get_cache_alignment()),
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GFP_KERNEL);
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if (!slv)
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return -ENOMEM;
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|
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spi_set_ctldata(spi, slv);
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ret = bcm2835_spi_setup_dma(ctlr, spi, bs, slv);
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if (ret)
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goto err_cleanup;
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}
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/*
|
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|
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@ -1212,20 +1240,19 @@ static int bcm2835_spi_setup(struct spi_device *spi)
|
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cs |= BCM2835_SPI_CS_CPOL;
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if (spi->mode & SPI_CPHA)
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cs |= BCM2835_SPI_CS_CPHA;
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bs->prepare_cs[spi->chip_select] = cs;
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slv->prepare_cs = cs;
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/*
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* Precalculate SPI slave's CS register value to clear RX FIFO
|
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* in case of a TX-only DMA transfer.
|
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*/
|
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if (ctlr->dma_rx) {
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bs->clear_rx_cs[spi->chip_select] = cs |
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BCM2835_SPI_CS_TA |
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BCM2835_SPI_CS_DMAEN |
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BCM2835_SPI_CS_CLEAR_RX;
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slv->clear_rx_cs = cs | BCM2835_SPI_CS_TA |
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BCM2835_SPI_CS_DMAEN |
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BCM2835_SPI_CS_CLEAR_RX;
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dma_sync_single_for_device(ctlr->dma_rx->device->dev,
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bs->clear_rx_addr,
|
||||
sizeof(bs->clear_rx_cs),
|
||||
slv->clear_rx_addr,
|
||||
sizeof(u32),
|
||||
DMA_TO_DEVICE);
|
||||
}
|
||||
|
||||
|
|
@ -1247,7 +1274,8 @@ static int bcm2835_spi_setup(struct spi_device *spi)
|
|||
*/
|
||||
dev_err(&spi->dev,
|
||||
"setup: only two native chip-selects are supported\n");
|
||||
return -EINVAL;
|
||||
ret = -EINVAL;
|
||||
goto err_cleanup;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1268,14 +1296,20 @@ static int bcm2835_spi_setup(struct spi_device *spi)
|
|||
DRV_NAME,
|
||||
GPIO_LOOKUP_FLAGS_DEFAULT,
|
||||
GPIOD_OUT_LOW);
|
||||
if (IS_ERR(spi->cs_gpiod))
|
||||
return PTR_ERR(spi->cs_gpiod);
|
||||
if (IS_ERR(spi->cs_gpiod)) {
|
||||
ret = PTR_ERR(spi->cs_gpiod);
|
||||
goto err_cleanup;
|
||||
}
|
||||
|
||||
/* and set up the "mode" and level */
|
||||
dev_info(&spi->dev, "setting up native-CS%i to use GPIO\n",
|
||||
spi->chip_select);
|
||||
|
||||
return 0;
|
||||
|
||||
err_cleanup:
|
||||
bcm2835_spi_cleanup(spi);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int bcm2835_spi_probe(struct platform_device *pdev)
|
||||
|
|
@ -1284,8 +1318,7 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
|
|||
struct bcm2835_spi *bs;
|
||||
int err;
|
||||
|
||||
ctlr = devm_spi_alloc_master(&pdev->dev, ALIGN(sizeof(*bs),
|
||||
dma_get_cache_alignment()));
|
||||
ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*bs));
|
||||
if (!ctlr)
|
||||
return -ENOMEM;
|
||||
|
||||
|
|
@ -1296,6 +1329,7 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
|
|||
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
ctlr->num_chipselect = 3;
|
||||
ctlr->setup = bcm2835_spi_setup;
|
||||
ctlr->cleanup = bcm2835_spi_cleanup;
|
||||
ctlr->transfer_one = bcm2835_spi_transfer_one;
|
||||
ctlr->handle_err = bcm2835_spi_handle_err;
|
||||
ctlr->prepare_message = bcm2835_spi_prepare_message;
|
||||
|
|
|
|||
Loading…
Reference in a new issue