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arm64: tegra: Add missing DFLL reset on Tegra210
commit0017f2c856
upstream. Commit4782c0a5dd
("clk: tegra: Don't deassert reset on enabling clocks") removed deassertion of reset lines when enabling peripheral clocks. This breaks the initialization of the DFLL driver which relied on this behaviour. In order to be able to fix this, add the corresponding reset to the DT. Tested on Google Pixel C. Cc: stable@vger.kernel.org Fixes:4782c0a5dd
("clk: tegra: Don't deassert reset on enabling clocks") Signed-off-by: Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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1 changed files with 3 additions and 2 deletions
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@ -1366,8 +1366,9 @@ dfll: clock@70110000 {
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<&tegra_car TEGRA210_CLK_DFLL_REF>,
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<&tegra_car TEGRA210_CLK_I2C5>;
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clock-names = "soc", "ref", "i2c";
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resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>;
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reset-names = "dvco";
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resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>,
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<&tegra_car 155>;
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reset-names = "dvco", "dfll";
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#clock-cells = <0>;
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clock-output-names = "dfllCPU_out";
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status = "disabled";
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