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arm64: Implement branch predictor hardening for Falkor
Falkor is susceptible to branch predictor aliasing and can theoretically be attacked by malicious code. This patch implements a mitigation for these attacks, preventing any malicious entries from affecting other victim contexts. Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org> [will: fix label name when !CONFIG_KVM and remove references to MIDR_FALKOR] Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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6 changed files with 70 additions and 3 deletions
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@ -43,7 +43,8 @@
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#define ARM64_SVE 22
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#define ARM64_UNMAP_KERNEL_AT_EL0 23
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#define ARM64_HARDEN_BRANCH_PREDICTOR 24
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#define ARM64_HARDEN_BP_POST_GUEST_EXIT 25
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#define ARM64_NCAPS 25
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#define ARM64_NCAPS 26
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#endif /* __ASM_CPUCAPS_H */
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@ -68,6 +68,8 @@ extern u32 __kvm_get_mdcr_el2(void);
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extern u32 __init_stage2_translation(void);
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extern void __qcom_hyp_sanitize_btac_predictors(void);
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#endif
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#endif /* __ARM_KVM_ASM_H__ */
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@ -77,3 +77,11 @@ ENTRY(__psci_hyp_bp_inval_start)
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ldp x0, x1, [sp, #(16 * 8)]
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add sp, sp, #(8 * 18)
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ENTRY(__psci_hyp_bp_inval_end)
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ENTRY(__qcom_hyp_sanitize_link_stack_start)
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stp x29, x30, [sp, #-16]!
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.rept 16
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bl . + 4
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.endr
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ldp x29, x30, [sp], #16
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ENTRY(__qcom_hyp_sanitize_link_stack_end)
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@ -54,6 +54,8 @@ DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
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#ifdef CONFIG_KVM
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extern char __psci_hyp_bp_inval_start[], __psci_hyp_bp_inval_end[];
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extern char __qcom_hyp_sanitize_link_stack_start[];
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extern char __qcom_hyp_sanitize_link_stack_end[];
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static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
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const char *hyp_vecs_end)
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@ -96,8 +98,10 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
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spin_unlock(&bp_lock);
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}
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#else
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#define __psci_hyp_bp_inval_start NULL
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#define __psci_hyp_bp_inval_end NULL
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#define __psci_hyp_bp_inval_start NULL
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#define __psci_hyp_bp_inval_end NULL
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#define __qcom_hyp_sanitize_link_stack_start NULL
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#define __qcom_hyp_sanitize_link_stack_end NULL
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static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
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const char *hyp_vecs_start,
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@ -138,6 +142,29 @@ static int enable_psci_bp_hardening(void *data)
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return 0;
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}
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static void qcom_link_stack_sanitization(void)
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{
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u64 tmp;
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asm volatile("mov %0, x30 \n"
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".rept 16 \n"
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"bl . + 4 \n"
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".endr \n"
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"mov x30, %0 \n"
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: "=&r" (tmp));
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}
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static int qcom_enable_link_stack_sanitization(void *data)
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{
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const struct arm64_cpu_capabilities *entry = data;
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install_bp_hardening_cb(entry, qcom_link_stack_sanitization,
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__qcom_hyp_sanitize_link_stack_start,
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__qcom_hyp_sanitize_link_stack_end);
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return 0;
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}
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#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
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#define MIDR_RANGE(model, min, max) \
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@ -302,6 +329,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
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.enable = enable_psci_bp_hardening,
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},
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
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.enable = qcom_enable_link_stack_sanitization,
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},
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{
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.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
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},
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#endif
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{
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}
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@ -196,3 +196,15 @@ alternative_endif
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eret
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ENDPROC(__fpsimd_guest_restore)
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ENTRY(__qcom_hyp_sanitize_btac_predictors)
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/**
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* Call SMC64 with Silicon provider serviceID 23<<8 (0xc2001700)
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* 0xC2000000-0xC200FFFF: assigned to SiP Service Calls
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* b15-b0: contains SiP functionID
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*/
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movz x0, #0x1700
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movk x0, #0xc200, lsl #16
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smc #0
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ret
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ENDPROC(__qcom_hyp_sanitize_btac_predictors)
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@ -406,6 +406,14 @@ int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu)
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/* 0 falls through to be handled out of EL2 */
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}
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if (cpus_have_const_cap(ARM64_HARDEN_BP_POST_GUEST_EXIT)) {
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u32 midr = read_cpuid_id();
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/* Apply BTAC predictors mitigation to all Falkor chips */
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if ((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)
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__qcom_hyp_sanitize_btac_predictors();
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}
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fp_enabled = __fpsimd_enabled();
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__sysreg_save_guest_state(guest_ctxt);
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