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drm/nouveau/fifo/gf100-: recover from host mmu faults 

This has been on the TODO list for a while now, recovering from things
such as attempting to execute a push buffer or touch a semaphore in an
unmapped memory area.

The only thing required on the HW side here is that the offending
channel is removed from the runlist, and *not* a full reset of PFIFO.

This used to be a bit messier to handle before the rework to make use
of engine topology info, but is apparently now trivial.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2016-12-09 17:13:08 +10:00
parent a8f6cb7bb3
commit ec884f74f1
4 changed files with 29 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c
View File

@ -180,7 +180,8 @@ gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine,
list_del_init(&chan->head);
chan->killed = true;
fifo->recover.mask |= 1ULL << engine->subdev.index;
if (engine != &fifo->base.engine)
fifo->recover.mask |= 1ULL << engine->subdev.index;
schedule_work(&fifo->recover.work);
}

16
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c
View File

@ -743,14 +743,14 @@ gk104_fifo_fault_engine[] = {
{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
{ 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
{ 0x06, "SCHED" },
{ 0x07, "HOST0" },
{ 0x08, "HOST1" },
{ 0x09, "HOST2" },
{ 0x0a, "HOST3" },
{ 0x0b, "HOST4" },
{ 0x0c, "HOST5" },
{ 0x0d, "HOST6" },
{ 0x0e, "HOST7" },
{ 0x07, "HOST0", NULL, NVKM_ENGINE_FIFO },
{ 0x08, "HOST1", NULL, NVKM_ENGINE_FIFO },
{ 0x09, "HOST2", NULL, NVKM_ENGINE_FIFO },
{ 0x0a, "HOST3", NULL, NVKM_ENGINE_FIFO },
{ 0x0b, "HOST4", NULL, NVKM_ENGINE_FIFO },
{ 0x0c, "HOST5", NULL, NVKM_ENGINE_FIFO },
{ 0x0d, "HOST6", NULL, NVKM_ENGINE_FIFO },
{ 0x0e, "HOST7", NULL, NVKM_ENGINE_FIFO },
{ 0x0f, "HOSTSR" },
{ 0x10, "MSVLD", NULL, NVKM_ENGINE_MSVLD },
{ 0x11, "MSPPP", NULL, NVKM_ENGINE_MSPPP },

16
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c
View File

@ -32,14 +32,14 @@ gm107_fifo_fault_engine[] = {
{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
{ 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
{ 0x06, "SCHED" },
{ 0x07, "HOST0" },
{ 0x08, "HOST1" },
{ 0x09, "HOST2" },
{ 0x0a, "HOST3" },
{ 0x0b, "HOST4" },
{ 0x0c, "HOST5" },
{ 0x0d, "HOST6" },
{ 0x0e, "HOST7" },
{ 0x07, "HOST0", NULL, NVKM_ENGINE_FIFO },
{ 0x08, "HOST1", NULL, NVKM_ENGINE_FIFO },
{ 0x09, "HOST2", NULL, NVKM_ENGINE_FIFO },
{ 0x0a, "HOST3", NULL, NVKM_ENGINE_FIFO },
{ 0x0b, "HOST4", NULL, NVKM_ENGINE_FIFO },
{ 0x0c, "HOST5", NULL, NVKM_ENGINE_FIFO },
{ 0x0d, "HOST6", NULL, NVKM_ENGINE_FIFO },
{ 0x0e, "HOST7", NULL, NVKM_ENGINE_FIFO },
{ 0x0f, "HOSTSR" },
{ 0x13, "PERF" },
{ 0x17, "PMU" },

22
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c
View File

@ -30,17 +30,17 @@ gp100_fifo_fault_engine[] = {
{ 0x03, "IFB", NULL, NVKM_ENGINE_IFB },
{ 0x04, "BAR1", NULL, NVKM_SUBDEV_BAR },
{ 0x05, "BAR2", NULL, NVKM_SUBDEV_INSTMEM },
{ 0x06, "HOST0" },
{ 0x07, "HOST1" },
{ 0x08, "HOST2" },
{ 0x09, "HOST3" },
{ 0x0a, "HOST4" },
{ 0x0b, "HOST5" },
{ 0x0c, "HOST6" },
{ 0x0d, "HOST7" },
{ 0x0e, "HOST8" },
{ 0x0f, "HOST9" },
{ 0x10, "HOST10" },
{ 0x06, "HOST0", NULL, NVKM_ENGINE_FIFO },
{ 0x07, "HOST1", NULL, NVKM_ENGINE_FIFO },
{ 0x08, "HOST2", NULL, NVKM_ENGINE_FIFO },
{ 0x09, "HOST3", NULL, NVKM_ENGINE_FIFO },
{ 0x0a, "HOST4", NULL, NVKM_ENGINE_FIFO },
{ 0x0b, "HOST5", NULL, NVKM_ENGINE_FIFO },
{ 0x0c, "HOST6", NULL, NVKM_ENGINE_FIFO },
{ 0x0d, "HOST7", NULL, NVKM_ENGINE_FIFO },
{ 0x0e, "HOST8", NULL, NVKM_ENGINE_FIFO },
{ 0x0f, "HOST9", NULL, NVKM_ENGINE_FIFO },
{ 0x10, "HOST10", NULL, NVKM_ENGINE_FIFO },
{ 0x13, "PERF" },
{ 0x17, "PMU" },
{ 0x18, "PTP" },