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Code Issues Releases Wiki Activity

drm/amd/display: Refactor edp panel power sequencer(PPS) codes

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[Why & How]
Move extra panel power sequencer settings into panel_cofig struct.

Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Ian Chen <ian.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Ian Chen 2022-08-30 14:50:24 +08:00 committed by Alex Deucher
parent ba5c071298
commit eccff6cdde
6 changed files with 46 additions and 21 deletions
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11
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c
View file

@ -880,8 +880,17 @@ void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigne
void dm_helpers_init_panel_settings(
struct dc_context *ctx,
struct dc_panel_config *panel_config)
struct dc_panel_config *panel_config,
struct dc_sink *sink)
{
// Extra Panel Power Sequence
panel_config->pps.extra_t3_ms = sink->edid_caps.panel_patch.extra_t3_ms;
panel_config->pps.extra_t7_ms = sink->edid_caps.panel_patch.extra_t7_ms;
panel_config->pps.extra_delay_backlight_off = sink->edid_caps.panel_patch.extra_delay_backlight_off;
panel_config->pps.extra_post_t7_ms = 0;
panel_config->pps.extra_pre_t11_ms = 0;
panel_config->pps.extra_t12_ms = sink->edid_caps.panel_patch.extra_t12_ms;
panel_config->pps.extra_post_OUI_ms = 0;
// Feature DSC
panel_config->dsc.disable_dsc_edp = false;
panel_config->dsc.force_dsc_edp_policy = 0;

8
drivers/gpu/drm/amd/display/dc/core/dc_link.c
View file

@ -1308,7 +1308,7 @@ static bool detect_link_and_local_sink(struct dc_link *link,
if (link->connector_signal == SIGNAL_TYPE_EDP) {
// Init dc_panel_config
dm_helpers_init_panel_settings(dc_ctx, &link->panel_config);
dm_helpers_init_panel_settings(dc_ctx, &link->panel_config, sink);
// Override dc_panel_config if system has specific settings
dm_helpers_override_panel_settings(dc_ctx, &link->panel_config);
}
@ -1977,7 +1977,7 @@ static enum dc_status enable_link_dp(struct dc_state *state,
int i;
bool apply_seamless_boot_optimization = false;
uint32_t bl_oled_enable_delay = 50; // in ms
const uint32_t post_oui_delay = 30; // 30ms
uint32_t post_oui_delay = 30; // 30ms
/* Reduce link bandwidth between failed link training attempts. */
bool do_fallback = false;
@ -2024,8 +2024,10 @@ static enum dc_status enable_link_dp(struct dc_state *state,
// during mode switch we do DP_SET_POWER off then on, and OUI is lost
dpcd_set_source_specific_data(link);
if (link->dpcd_sink_ext_caps.raw != 0)
if (link->dpcd_sink_ext_caps.raw != 0) {
post_oui_delay += link->panel_config.pps.extra_post_OUI_ms;
msleep(post_oui_delay);
}
// similarly, mode switch can cause loss of cable ID
dpcd_write_cable_id_to_dprx(link);

10
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
View file

@ -7075,9 +7075,8 @@ void dp_enable_link_phy(
void edp_add_delay_for_T9(struct dc_link *link)
{
if (link->local_sink &&
link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off > 0)
udelay(link->local_sink->edid_caps.panel_patch.extra_delay_backlight_off * 1000);
if (link && link->panel_config.pps.extra_delay_backlight_off > 0)
udelay(link->panel_config.pps.extra_delay_backlight_off * 1000);
}
bool edp_receiver_ready_T9(struct dc_link *link)
@ -7133,9 +7132,8 @@ bool edp_receiver_ready_T7(struct dc_link *link)
} while (time_taken_in_ns < 50 * 1000000); //MAx T7 is 50ms
}
if (link->local_sink &&
link->local_sink->edid_caps.panel_patch.extra_t7_ms > 0)
udelay(link->local_sink->edid_caps.panel_patch.extra_t7_ms * 1000);
if (link && link->panel_config.pps.extra_t7_ms > 0)
udelay(link->panel_config.pps.extra_t7_ms * 1000);
return result;
}

10
drivers/gpu/drm/amd/display/dc/dc_link.h
View file

@ -117,6 +117,16 @@ struct psr_settings {
* Add a struct dc_panel_config under dc_link
*/
struct dc_panel_config {
// extra panel power sequence parameters
struct pps {
unsigned int extra_t3_ms;
unsigned int extra_t7_ms;
unsigned int extra_delay_backlight_off;
unsigned int extra_post_t7_ms;
unsigned int extra_pre_t11_ms;
unsigned int extra_t12_ms;
unsigned int extra_post_OUI_ms;
} pps;
// edp DSC
struct dsc {
bool disable_dsc_edp;

25
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View file

@ -722,7 +722,6 @@ void dce110_edp_wait_for_hpd_ready(
struct dc_context *ctx = link->ctx;
struct graphics_object_id connector = link->link_enc->connector;
struct gpio *hpd;
struct dc_sink *sink = link->local_sink;
bool edp_hpd_high = false;
uint32_t time_elapsed = 0;
uint32_t timeout = power_up ?
@ -755,9 +754,9 @@ void dce110_edp_wait_for_hpd_ready(
return;
}
if (sink != NULL) {
if (sink->edid_caps.panel_patch.extra_t3_ms > 0) {
int extra_t3_in_ms = sink->edid_caps.panel_patch.extra_t3_ms;
if (link != NULL) {
if (link->panel_config.pps.extra_t3_ms > 0) {
int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms;
msleep(extra_t3_in_ms);
}
@ -842,7 +841,7 @@ void dce110_edp_power_control(
/* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */
if (link->local_sink != NULL)
remaining_min_edp_poweroff_time_ms +=
link->local_sink->edid_caps.panel_patch.extra_t12_ms;
link->panel_config.pps.extra_t12_ms;
/* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */
if (dp_trace_get_edp_poweroff_timestamp(link) != 0) {
@ -946,7 +945,7 @@ void dce110_edp_wait_for_T12(
current_ts,
dp_trace_get_edp_poweroff_timestamp(link)), 1000000);
t12_duration += link->local_sink->edid_caps.panel_patch.extra_t12_ms; // Add extra T12
t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12
if (time_since_edp_poweroff_ms < t12_duration)
msleep(t12_duration - time_since_edp_poweroff_ms);
@ -965,6 +964,8 @@ void dce110_edp_backlight_control(
struct dc_context *ctx = link->ctx;
struct bp_transmitter_control cntl = { 0 };
uint8_t panel_instance;
unsigned int pre_T11_delay = OLED_PRE_T11_DELAY;
unsigned int post_T7_delay = OLED_POST_T7_DELAY;
if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
!= CONNECTOR_ID_EDP) {
@ -1043,8 +1044,10 @@ void dce110_edp_backlight_control(
link_transmitter_control(ctx->dc_bios, &cntl);
if (enable && link->dpcd_sink_ext_caps.bits.oled)
msleep(OLED_POST_T7_DELAY);
if (enable && link->dpcd_sink_ext_caps.bits.oled) {
post_T7_delay += link->panel_config.pps.extra_post_t7_ms;
msleep(post_T7_delay);
}
if (link->dpcd_sink_ext_caps.bits.oled ||
link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
@ -1066,8 +1069,10 @@ void dce110_edp_backlight_control(
DC_LOG_DC("edp_receiver_ready_T9 skipped\n");
}
if (!enable && link->dpcd_sink_ext_caps.bits.oled)
msleep(OLED_PRE_T11_DELAY);
if (!enable && link->dpcd_sink_ext_caps.bits.oled) {
pre_T11_delay += link->panel_config.pps.extra_pre_t11_ms;
msleep(pre_T11_delay);
}
}
void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)

3
drivers/gpu/drm/amd/display/dc/dm_helpers.h
View file

@ -173,7 +173,8 @@ void dm_helpers_smu_timeout(struct dc_context *ctx, unsigned int msg_id, unsigne
(result == 0x0)
void dm_helpers_init_panel_settings(
struct dc_context *ctx,
struct dc_panel_config *config);
struct dc_panel_config *config,
struct dc_sink *sink);
void dm_helpers_override_panel_settings(
struct dc_context *ctx,
struct dc_panel_config *config);