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PCI: Add a generic weak pcibios_align_resource()
Multiple architectures define this as a trivial function, and I'm adding another one as part of the RISC-V port. Add a __weak version of pcibios_align_resource() and delete the now-obselete ones in a handful of ports. The only functional change should be that a handful of ports used to export pcibios_fixup_bus(). Only some architectures export this, so I just dropped it. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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commit
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10 changed files with 13 additions and 69 deletions
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@ -7,12 +7,3 @@
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*/
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*/
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#include <linux/pci.h>
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#include <linux/pci.h>
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/*
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* We don't have to worry about legacy ISA devices, so nothing to do here
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*/
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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return res->start;
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}
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@ -22,15 +22,6 @@
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#include <linux/pci-ecam.h>
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#include <linux/pci-ecam.h>
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#include <linux/slab.h>
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#include <linux/slab.h>
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/*
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* We don't have to worry about legacy ISA devices, so nothing to do here
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*/
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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return res->start;
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}
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#ifdef CONFIG_ACPI
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#ifdef CONFIG_ACPI
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/*
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/*
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* Try to assign the IRQ number when probing a new device
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* Try to assign the IRQ number when probing a new device
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@ -411,13 +411,6 @@ pcibios_disable_device (struct pci_dev *dev)
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acpi_pci_irq_disable(dev);
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acpi_pci_irq_disable(dev);
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}
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}
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resource_size_t
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pcibios_align_resource (void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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return res->start;
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}
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/**
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/**
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* ia64_pci_get_legacy_mem - generic legacy mem routine
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* ia64_pci_get_legacy_mem - generic legacy mem routine
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* @bus: bus to get legacy memory base address for
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* @bus: bus to get legacy memory base address for
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@ -823,13 +823,6 @@ void pcibios_setup_bus_devices(struct pci_bus *bus)
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* but we want to try to avoid allocating at 0x2900-0x2bff
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* but we want to try to avoid allocating at 0x2900-0x2bff
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* which might have be mirrored at 0x0100-0x03ff..
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* which might have be mirrored at 0x0100-0x03ff..
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*/
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*/
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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return res->start;
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}
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EXPORT_SYMBOL(pcibios_align_resource);
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int pcibios_add_device(struct pci_dev *dev)
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int pcibios_add_device(struct pci_dev *dev)
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{
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{
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dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
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dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
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@ -94,9 +94,3 @@ void pcibios_fixup_bus(struct pci_bus *pbus)
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}
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}
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}
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}
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}
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}
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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return res->start;
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}
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@ -690,12 +690,6 @@ struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
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return bus;
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return bus;
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}
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}
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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return res->start;
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}
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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{
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u16 cmd, oldcmd;
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u16 cmd, oldcmd;
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@ -746,12 +746,6 @@ static void watchdog_reset() {
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}
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}
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#endif
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#endif
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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return res->start;
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}
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int pcibios_enable_device(struct pci_dev *pdev, int mask)
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int pcibios_enable_device(struct pci_dev *pdev, int mask)
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{
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{
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return 0;
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return 0;
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@ -66,16 +66,6 @@ static int pci_scan_flags[TILE_NUM_PCIE];
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static struct pci_ops tile_cfg_ops;
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static struct pci_ops tile_cfg_ops;
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/*
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* We don't need to worry about the alignment of resources.
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*/
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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return res->start;
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}
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EXPORT_SYMBOL(pcibios_align_resource);
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/*
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/*
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* Open a FD to the hypervisor PCI device.
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* Open a FD to the hypervisor PCI device.
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*
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*
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@ -108,15 +108,6 @@ static struct pci_ops tile_cfg_ops;
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/* Mask of CPUs that should receive PCIe interrupts. */
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/* Mask of CPUs that should receive PCIe interrupts. */
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static struct cpumask intr_cpus_map;
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static struct cpumask intr_cpus_map;
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/* We don't need to worry about the alignment of resources. */
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size,
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resource_size_t align)
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{
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return res->start;
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}
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EXPORT_SYMBOL(pcibios_align_resource);
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/*
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/*
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* Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #.
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* Pick a CPU to receive and handle the PCIe interrupts, based on the IRQ #.
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* For now, we simply send interrupts to non-dataplane CPUs.
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* For now, we simply send interrupts to non-dataplane CPUs.
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@ -234,6 +234,19 @@ static int pci_revert_fw_address(struct resource *res, struct pci_dev *dev,
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return 0;
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return 0;
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}
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}
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/*
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* We don't have to worry about legacy ISA devices, so nothing to do here.
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* This is marked as __weak because multiple architectures define it; it should
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* eventually go away.
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*/
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resource_size_t __weak pcibios_align_resource(void *data,
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const struct resource *res,
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resource_size_t size,
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resource_size_t align)
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{
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return res->start;
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}
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static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
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static int __pci_assign_resource(struct pci_bus *bus, struct pci_dev *dev,
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int resno, resource_size_t size, resource_size_t align)
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int resno, resource_size_t size, resource_size_t align)
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{
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{
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