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imx device tree changes for 3.11: 

* A bunch of new board additions, imx6sl-evk, vf610-twr, imx53-tx53,
   imx53-m53evk and imx27-phytec-phycore
 * Various pinctrl setting updates and additions
 * Enable various on board peripherals, usb, audio, nor, display etc.
 * Configure L2 cache data and tag latency from device tree
 * Add imx-weim bus driver
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQEcBAABAgAGBQJRvsoqAAoJEFBXWFqHsHzOWCsIAIhbVAz9Q/HvRrrT2/viiu5G
 S6/O16PbTqCmRPOgjnABGNOzRxo94/abhYT7gbGDz/zqAK2wEzEtUMwX8SXJbvl2
 ynt4oX/QTgeQsZZXW+dCdet6XiBSJwfbFFo0c01pCBvPb7os739pO3u3CUvNeqKx
 vsEfiq190PSPVL0FdfyLpQB+64ApUB1L/Ez9BaWmJjQYN2LWM0lxyvbC0SPo1vrw
 eb8NJ7qz/qq3zXCKgD8LEvkfal4ZsezPYzap1sqKl1+T2aN4CsgzYaRra/wDv7BC
 0ssW3+11StrwrbdwOEQRwiSU15fc9ckVldoFGlB+9HKTZxh80u0HmZRvFWbWo0E=
 =jngF
 -----END PGP SIGNATURE-----

Merge tag 'imx-dt-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt

From Shawn Guo:

imx device tree changes for 3.11:

* A bunch of new board additions, imx6sl-evk, vf610-twr, imx53-tx53,
  imx53-m53evk and imx27-phytec-phycore
* Various pinctrl setting updates and additions
* Enable various on board peripherals, usb, audio, nor, display etc.
* Configure L2 cache data and tag latency from device tree
* Add imx-weim bus driver

* tag 'imx-dt-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6: (82 commits)
  ARM: dts: imx27: Add VPU devicetree node
  ARM: mxc: fix gpio-ranges for VF610
  ARM: dtsi: imx6qdl-sabresd: Enable WM8962 audio support
  ARM: dtsi: imx6qdl-sabresd: Enable SSI2 and AUDMUX
  ARM: dtsi: imx6qdl-sabresd: Add WM8962 CODEC support
  ARM: dtsi: imx6qdl-sabresd: add a fixed regulator for WM8962
  ARM: dtsi: imx6dl: Add a pinctrl for AUDMUX
  ARM: dtsi: imx6q/imx6dl: Add a pinctrl for I2C1
  ARM: dts: imx6qdl-sabresd: add clko1 iomux configuration
  ARM: dts: Phytec imx6q pfla02 and pbab01 support
  ARM: dts: imx6q: Add pinctrl for usdhc2 and enet
  ARM: dts: imx27-phytec-phycore-rdk: Add MTD name for NOR flash
  ARM: dts: imx27-phytec-phycore-rdk: Add SDHC support
  ARM: dts: i.MX27: Add SDHC devicetree nodes
  ARM: dts: i.MX27: Add DMA devicetree node
  ARM: dts: imx6qdl-sabreauto: enable the WEIM NOR
  ARM: dts: imx6dl: add pinctrls for WEIM NOR
  ARM: dts: imx6q: add pinctrls for WEIM NOR
  ARM: dts: imx6qdl: add more information for WEIM
  ARM: dts: imx6q{dl}: fix the pin conflict between SPI and WEIM
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2013-06-20 02:11:29 +02:00
parent f25a4d68f8 93b331cec9
commit ed2ca6ee4b
36 changed files with 4036 additions and 171 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
Documentation/devicetree/bindings/bus/imx-weim.txt Normal file
View File

@ -0,0 +1,49 @@
Device tree bindings for i.MX Wireless External Interface Module (WEIM)
The term "wireless" does not imply that the WEIM is literally an interface
without wires. It simply means that this module was originally designed for
wireless and mobile applications that use low-power technology.
The actual devices are instantiated from the child nodes of a WEIM node.
Required properties:
- compatible: Should be set to "fsl,imx6q-weim"
- reg: A resource specifier for the register space
(see the example below)
- clocks: the clock, see the example below.
- #address-cells: Must be set to 2 to allow memory address translation
- #size-cells: Must be set to 1 to allow CS address passing
- ranges: Must be set up to reflect the memory layout with four
integer values for each chip-select line in use:
<cs-number> 0 <physical address of mapping> <size>
Timing property for child nodes. It is mandatory, not optional.
- fsl,weim-cs-timing: The timing array, contains 6 timing values for the
child node. We can get the CS index from the child
node's "reg" property. This property contains the values
for the registers EIM_CSnGCR1, EIM_CSnGCR2, EIM_CSnRCR1,
EIM_CSnRCR2, EIM_CSnWCR1, EIM_CSnWCR2 in this order.
Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
weim: weim@021b8000 {
compatible = "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
clocks = <&clks 196>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>;
nor@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x02000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
0x0000c000 0x1404a38e 0x00000000>;
};
};

2
Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
View File

@ -58,7 +58,7 @@ Some requirements for using fsl,imx-pinctrl binding:
Examples:
usdhc@0219c000 { /* uSDHC4 */
fsl,card-wired;
non-removable;
vmmc-supply = <&reg_3p3v>;
status = "okay";
pinctrl-names = "default";

9
arch/arm/boot/dts/Makefile
View File

@ -107,13 +107,15 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx27-apf27.dtb \
imx27-apf27dev.dtb \
imx27-pdk.dtb \
imx27-phytec-phycore.dtb \
imx27-phytec-phycore-som.dtb \
imx27-phytec-phycore-rdk.dtb \
imx31-bug.dtb \
imx51-apf51.dtb \
imx51-apf51dev.dtb \
imx51-babbage.dtb \
imx53-ard.dtb \
imx53-evk.dtb \
imx53-m53evk.dtb \
imx53-mba53.dtb \
imx53-qsb.dtb \
imx53-smd.dtb \
@ -121,10 +123,13 @@ dtb-$(CONFIG_ARCH_MXC) += \
imx6dl-sabresd.dtb \
imx6dl-wandboard.dtb \
imx6q-arm2.dtb \
imx6q-phytec-pbab01.dtb \
imx6q-sabreauto.dtb \
imx6q-sabrelite.dtb \
imx6q-sabresd.dtb \
imx6q-sbc6x.dtb
imx6q-sbc6x.dtb \
imx6sl-evk.dtb \
vf610-twr.dtb
dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
imx23-olinuxino.dtb \
imx23-stmp378x_devb.dtb \

37
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts Normal file
View File

@ -0,0 +1,37 @@
/*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx27-phytec-phycore-som.dts"
/ {
model = "Phytec pcm970";
compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27";
};
&cspi1 {
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>;
};
&sdhci2 {
bus-width = <4>;
cd-gpios = <&gpio3 29 0>;
wp-gpios = <&gpio3 28 0>;
vmmc-supply = <&vmmc1_reg>;
status = "okay";
};
&uart1 {
fsl,uart-has-rtscts;
};
&uart2 {
fsl,uart-has-rtscts;
status = "okay";
};

179
arch/arm/boot/dts/imx27-phytec-phycore-som.dts Normal file
View File

@ -0,0 +1,179 @@
/*
* Copyright 2012 Sascha Hauer, Pengutronix
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx27.dtsi"
/ {
model = "Phytec pcm038";
compatible = "phytec,imx27-pcm038", "fsl,imx27";
memory {
reg = <0x0 0x0>;
};
soc {
aipi@10000000 { /* aipi1 */
serial@1000a000 {
status = "okay";
};
i2c@1001d000 {
clock-frequency = <400000>;
status = "okay";
at24@52 {
compatible = "at,24c32";
pagesize = <32>;
reg = <0x52>;
};
pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
lm75@4a {
compatible = "national,lm75";
reg = <0x4a>;
};
};
};
aipi@10020000 { /* aipi2 */
ethernet@1002b000 {
phy-reset-gpios = <&gpio3 30 0>;
status = "okay";
};
};
};
nor_flash@c0000000 {
compatible = "cfi-flash";
bank-width = <2>;
reg = <0xc0000000 0x02000000>;
linux,mtd-name = "physmap-flash.0";
#address-cells = <1>;
#size-cells = <1>;
};
};
&cspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 28 0>;
status = "okay";
pmic: mc13783@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mc13783";
spi-max-frequency = <20000000>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <23 0x4>;
fsl,mc13xxx-uses-adc;
fsl,mc13xxx-uses-rtc;
regulators {
sw1a_reg: sw1a {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
sw1b_reg: sw1b {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
sw2a_reg: sw2a {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
sw2b_reg: sw2b {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
sw3_reg: sw3 {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
vaudio_reg: vaudio {
regulator-always-on;
regulator-boot-on;
};
violo_reg: violo {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
viohi_reg: viohi {
regulator-always-on;
regulator-boot-on;
};
vgen_reg: vgen {
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
};
vcam_reg: vcam {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
vrf1_reg: vrf1 {
regulator-min-microvolt = <2775000>;
regulator-max-microvolt = <2775000>;
regulator-always-on;
regulator-boot-on;
};
vrf2_reg: vrf2 {
regulator-min-microvolt = <2775000>;
regulator-max-microvolt = <2775000>;
regulator-always-on;
regulator-boot-on;
};
vmmc1_reg: vmmc1 {
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3000000>;
};
gpo1_reg: gpo1 { };
pwgt1spi_reg: pwgt1spi {
regulator-always-on;
};
};
};
};
&nfc {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
status = "okay";
};

79
arch/arm/boot/dts/imx27-phytec-phycore.dts
View File

@ -1,79 +0,0 @@
/*
* Copyright 2012 Sascha Hauer, Pengutronix
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx27.dtsi"
/ {
model = "Phytec pcm038";
compatible = "phytec,imx27-pcm038", "fsl,imx27";
memory {
reg = <0x0 0x0>;
};
soc {
aipi@10000000 { /* aipi1 */
serial@1000a000 {
fsl,uart-has-rtscts;
status = "okay";
};
serial@1000b000 {
fsl,uart-has-rtscts;
status = "okay";
};
serial@1000c000 {
fsl,uart-has-rtscts;
status = "okay";
};
i2c@1001d000 {
clock-frequency = <400000>;
status = "okay";
at24@52 {
compatible = "at,24c32";
pagesize = <32>;
reg = <0x52>;
};
pcf8563@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
lm75@4a {
compatible = "national,lm75";
reg = <0x4a>;
};
};
};
aipi@10020000 { /* aipi2 */
ethernet@1002b000 {
status = "okay";
};
};
};
nor_flash@c0000000 {
compatible = "cfi-flash";
bank-width = <2>;
reg = <0xc0000000 0x02000000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
&nfc {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
status = "okay";
};

80
arch/arm/boot/dts/imx27.dtsi
View File

@ -25,6 +25,9 @@
gpio3 = &gpio4;
gpio4 = &gpio5;
gpio5 = &gpio6;
spi0 = &cspi1;
spi1 = &cspi2;
spi2 = &cspi3;
};
avic: avic-interrupt-controller@e0000000 {
@ -58,6 +61,16 @@
reg = <0x10000000 0x20000>;
ranges;
dma: dma@10001000 {
compatible = "fsl,imx27-dma";
reg = <0x10001000 0x1000>;
interrupts = <32>;
clocks = <&clks 50>, <&clks 70>;
clock-names = "ipg", "ahb";
#dma-cells = <1>;
#dma-channels = <16>;
};
wdog: wdog@10002000 {
compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
reg = <0x10002000 0x1000>;
@ -89,6 +102,14 @@
clock-names = "ipg", "per";
};
pwm0: pwm@10006000 {
compatible = "fsl,imx27-pwm";
reg = <0x10006000 0x1000>;
interrupts = <23>;
clocks = <&clks 34>, <&clks 61>;
clock-names = "ipg", "per";
};
uart1: serial@1000a000 {
compatible = "fsl,imx27-uart", "fsl,imx21-uart";
reg = <0x1000a000 0x1000>;
@ -157,6 +178,28 @@
status = "disabled";
};
sdhci1: sdhci@10013000 {
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
reg = <0x10013000 0x1000>;
interrupts = <11>;
clocks = <&clks 30>, <&clks 60>;
clock-names = "ipg", "per";
dmas = <&dma 7>;
dma-names = "rx-tx";
status = "disabled";
};
sdhci2: sdhci@10014000 {
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
reg = <0x10014000 0x1000>;
interrupts = <10>;
clocks = <&clks 29>, <&clks 60>;
clock-names = "ipg", "per";
dmas = <&dma 6>;
dma-names = "rx-tx";
status = "disabled";
};
gpio1: gpio@10015000 {
compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
reg = <0x10015000 0x100>;
@ -272,6 +315,17 @@
status = "disabled";
};
sdhci3: sdhci@1001e000 {
compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
reg = <0x1001e000 0x1000>;
interrupts = <9>;
clocks = <&clks 28>, <&clks 60>;
clock-names = "ipg", "per";
dmas = <&dma 36>;
dma-names = "rx-tx";
status = "disabled";
};
gpt6: timer@1001f000 {
compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
reg = <0x1001f000 0x1000>;
@ -288,6 +342,21 @@
reg = <0x10020000 0x20000>;
ranges;
coda: coda@10023000 {
compatible = "fsl,imx27-vpu";
reg = <0x10023000 0x0200>;
interrupts = <53>;
clocks = <&clks 57>, <&clks 66>;
clock-names = "per", "ahb";
iram = <&iram>;
};
clks: ccm@10027000{
compatible = "fsl,imx27-ccm";
reg = <0x10027000 0x1000>;
#clock-cells = <1>;
};
fec: ethernet@1002b000 {
compatible = "fsl,imx27-fec";
reg = <0x1002b000 0x4000>;
@ -296,19 +365,16 @@
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
clks: ccm@10027000{
compatible = "fsl,imx27-ccm";
reg = <0x10027000 0x1000>;
#clock-cells = <1>;
};
};
iram: iram@ffff4c00 {
compatible = "mmio-sram";
reg = <0xffff4c00 0xb400>;
};
nfc: nand@d8000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx27-nand";
reg = <0xd8000000 0x1000>;
interrupts = <29>;

7
arch/arm/boot/dts/imx51-apf51.dts
View File

@ -45,6 +45,13 @@
status = "okay";
};
&nfc {
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_2>;

23
arch/arm/boot/dts/imx51.dtsi
View File

@ -175,10 +175,20 @@
};
};
usbphy0: usbphy@0 {
compatible = "usb-nop-xceiv";
clocks = <&clks 124>;
clock-names = "main_clk";
status = "okay";
};
usbotg: usb@73f80000 {
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80000 0x0200>;
interrupts = <18>;
clocks = <&clks 108>;
fsl,usbmisc = <&usbmisc 0>;
fsl,usbphy = <&usbphy0>;
status = "disabled";
};
@ -186,6 +196,8 @@
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80200 0x0200>;
interrupts = <14>;
clocks = <&clks 108>;
fsl,usbmisc = <&usbmisc 1>;
status = "disabled";
};
@ -193,6 +205,8 @@
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80400 0x0200>;
interrupts = <16>;
clocks = <&clks 108>;
fsl,usbmisc = <&usbmisc 2>;
status = "disabled";
};
@ -200,9 +214,18 @@
compatible = "fsl,imx51-usb", "fsl,imx27-usb";
reg = <0x73f80600 0x0200>;
interrupts = <17>;
clocks = <&clks 108>;
fsl,usbmisc = <&usbmisc 3>;
status = "disabled";
};
usbmisc: usbmisc@73f80800 {
#index-cells = <1>;
compatible = "fsl,imx51-usbmisc";
reg = <0x73f80800 0x200>;
clocks = <&clks 108>;
};
gpio1: gpio@73f84000 {
compatible = "fsl,imx51-gpio", "fsl,imx35-gpio";
reg = <0x73f84000 0x4000>;

259
arch/arm/boot/dts/imx53-m53evk.dts Normal file
View File

@ -0,0 +1,259 @@
/*
* Copyright (C) 2013 Marek Vasut <marex@denx.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx53.dtsi"
/ {
model = "DENX M53EVK";
compatible = "denx,imx53-m53evk", "fsl,imx53";
memory {
reg = <0x70000000 0x20000000>;
};
soc {
display@di1 {
compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 1>;
interface-pix-fmt = "bgr666";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp2_1>;
display-timings {
800x480p60 {
native-mode;
clock-frequency = <31500000>;
hactive = <800>;
vactive = <480>;
hfront-porch = <40>;
hback-porch = <88>;
hsync-len = <128>;
vback-porch = <33>;
vfront-porch = <9>;
vsync-len = <3>;
vsync-active = <1>;
};
};
};
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 3000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pin_gpio>;
user1 {
label = "user1";
gpios = <&gpio2 8 0>;
linux,default-trigger = "heartbeat";
};
user2 {
label = "user2";
gpios = <&gpio2 9 0>;
linux,default-trigger = "heartbeat";
};
};
regulators {
compatible = "simple-bus";
reg_3p2v: 3p2v {
compatible = "regulator-fixed";
regulator-name = "3P2V";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
};
sound {
compatible = "fsl,imx53-m53evk-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx53-m53evk-sgtl5000";
ssi-controller = <&ssi2>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"LINE_IN", "Line In Jack",
"Headphone Jack", "HP_OUT",
"Ext Spk", "LINE_OUT";
mux-int-port = <2>;
mux-ext-port = <4>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_2>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_3>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2_1>;
status = "okay";
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_1>;
cd-gpios = <&gpio1 1 0>;
wp-gpios = <&gpio1 9 0>;
status = "okay";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
status = "okay";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_2>;
status = "okay";
sgtl5000: codec@0a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
clocks = <&clks 150>;
};
};
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2_2>;
clock-frequency = <400000>;
status = "okay";
stmpe610@41 {
compatible = "st,stmpe610";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x41>;
id = <0>;
blocks = <0x5>;
interrupts = <6 0x0>;
interrupt-parent = <&gpio7>;
irq-trigger = <0x1>;
stmpe_touchscreen {
compatible = "stmpe,ts";
reg = <0>;
ts,sample-time = <4>;
ts,mod-12b = <1>;
ts,ref-sel = <0>;
ts,adc-freq = <1>;
ts,ave-ctrl = <3>;
ts,touch-det-delay = <3>;
ts,settling = <4>;
ts,fraction-z = <7>;
ts,i-drive = <1>;
};
};
eeprom: eeprom@50 {
compatible = "atmel,24c128";
reg = <0x50>;
pagesize = <32>;
};
rtc: rtc@68 {
compatible = "stm,m41t62";
reg = <0x68>;
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_1>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
>;
};
led_pin_gpio: led_gpio@0 {
fsl,pins = <
MX53_PAD_PATA_DATA8__GPIO2_8 0x80000000
MX53_PAD_PATA_DATA9__GPIO2_9 0x80000000
>;
};
};
};
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand_1>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1_1>;
status = "okay";
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_2>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_1>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1>;
status = "okay";
};

175
arch/arm/boot/dts/imx53-mba53.dts
View File

@ -16,27 +16,81 @@
/ {
model = "TQ MBa53 starter kit";
compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
reg_backlight: fixed@0 {
compatible = "regulator-fixed";
regulator-name = "lcd-supply";
gpio = <&gpio2 5 0>;
startup-delay-us = <5000>;
enable-active-low;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm2 0 50000 0 0>;
brightness-levels = <0 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100>;
default-brightness-level = <10>;
enable-gpios = <&gpio7 7 0>;
power-supply = <&reg_backlight>;
};
disp1: display@disp1 {
compatible = "fsl,imx-parallel-display";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp1_1>;
crtcs = <&ipu 1>;
interface-pix-fmt = "rgb24";
status = "disabled";
};
reg_3p2v: 3p2v {
compatible = "regulator-fixed";
regulator-name = "3P2V";
regulator-min-microvolt = <3200000>;
regulator-max-microvolt = <3200000>;
regulator-always-on;
};
sound {
compatible = "tq,imx53-mba53-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx53-mba53-sgtl5000";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
mux-int-port = <2>;
mux-ext-port = <5>;
};
};
&ldb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds1_1>;
status = "disabled";
};
&iomuxc {
lvds1 {
pinctrl_lvds1_1: lvds1-grp1 {
fsl,pins = <
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x10000
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x10000
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x10000
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x10000
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x10000
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
>;
};
pinctrl_lvds1_2: lvds1-grp2 {
fsl,pins = <
MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x10000
MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x10000
MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x10000
MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x10000
MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x10000
MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
>;
};
};
@ -44,33 +98,44 @@
disp1 {
pinctrl_disp1_1: disp1-grp1 {
fsl,pins = <
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x10000 /* DISP1_DRDY */
MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x10000 /* DISP1_HSYNC */
MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x10000 /* DISP1_VSYNC */
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x10000
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x10000
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x10000
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x10000
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x10000
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x10000
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x10000
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x10000
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x10000
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x10000
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x10000
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x10000
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x10000
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x10000
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x10000
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x10000
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x10000
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x10000
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x10000
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x10000
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x10000
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x10000
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x10000
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x10000
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x80000000 /* DISP1_DRDY */
MX53_PAD_EIM_D23__IPU_DI1_PIN2 0x80000000 /* DISP1_HSYNC */
MX53_PAD_EIM_EB3__IPU_DI1_PIN3 0x80000000 /* DISP1_VSYNC */
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x80000000
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x80000000
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x80000000
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x80000000
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x80000000
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x80000000
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x80000000
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x80000000
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x80000000
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x80000000
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x80000000
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x80000000
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x80000000
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x80000000
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x80000000
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x80000000
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x80000000
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x80000000
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x80000000
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x80000000
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x80000000
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x80000000
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x80000000
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x80000000
>;
};
};
tve {
pinctrl_vga_sync_1: vgasync-grp1 {
fsl,pins = <
/* VGA_VSYNC, HSYNC with max drive strength */
MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0xe6
MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0xe6
>;
};
};
@ -80,16 +145,27 @@
status = "okay";
};
&audmux {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
};
&i2c2 {
codec: sgtl5000@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks 150>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
};
expander: pca9554@20 {
compatible = "pca9554";
reg = <0x20>;
interrupts = <109>;
#gpio-cells = <2>;
gpio-controller;
};
sensor2: lm75@49 {
@ -99,6 +175,7 @@
};
&fec {
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
};
@ -114,10 +191,24 @@
status = "okay";
};
&usbotg {
dr_mode = "host";
status = "okay";
};
&usbh1 {
status = "okay";
};
&uart1 {
status = "okay";
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
&uart2 {
status = "okay";
};
@ -133,3 +224,13 @@
&i2c3 {
status = "okay";
};
&tve {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vga_sync_1>;
ddc = <&i2c3>;
fsl,tve-mode = "vga";
fsl,hsync-pin = <4>;
fsl,vsync-pin = <6>;
status = "okay";
};

36
arch/arm/boot/dts/imx53-qsb.dts
View File

@ -21,6 +21,33 @@
reg = <0x70000000 0x40000000>;
};
display@di0 {
compatible = "fsl,imx-parallel-display";
crtcs = <&ipu 0>;
interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp0_1>;
status = "disabled";
display-timings {
claawvga {
native-mode;
clock-frequency = <27000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <60>;
vback-porch = <10>;
vfront-porch = <10>;
hsync-len = <20>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
gpio-keys {
compatible = "gpio-keys";
@ -147,6 +174,7 @@
reg = <0x0a>;
VDDA-supply = <&reg_3p2v>;
VDDIO-supply = <&reg_3p2v>;
clocks = <&clks 150>;
};
};
@ -268,3 +296,11 @@
phy-reset-gpios = <&gpio7 6 0>;
status = "okay";
};
&usbh1 {
status = "okay";
};
&usbotg {
status = "okay";
};

45
arch/arm/boot/dts/imx53-tqma53.dtsi
View File

@ -35,7 +35,9 @@
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
pinctrl-0 = <&pinctrl_esdhc2_1>,
<&pinctrl_tqma53_esdhc2_2>;
vmmc-supply = <&reg_3p3v>;
wp-gpios = <&gpio1 2 0>;
cd-gpios = <&gpio1 4 0>;
status = "disabled";
@ -69,14 +71,22 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
esdhc2_2 {
pinctrl_tqma53_esdhc2_2: esdhc2-tqma53-grp2 {
fsl,pins = <
MX53_PAD_GPIO_4__GPIO1_4 0x80000000 /* SD2_CD */
MX53_PAD_GPIO_2__GPIO1_2 0x80000000 /* SD2_WP */
>;
};
};
i2s {
pinctrl_i2s_1: i2s-grp1 {
fsl,pins = <
MX53_PAD_GPIO_19__GPIO4_5 0x10000 /* I2S_MCLK */
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x10000 /* I2S_SCLK */
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x10000 /* I2S_DOUT */
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x10000 /* I2S_LRCLK */
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x10000 /* I2S_DIN */
MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000 /* I2S_SCLK */
MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000 /* I2S_DOUT */
MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000 /* I2S_LRCLK */
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000 /* I2S_DIN */
>;
};
};
@ -84,16 +94,17 @@
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX53_PAD_EIM_CS1__IPU_DI1_PIN6 0x10000 /* VSYNC */
MX53_PAD_EIM_DA15__IPU_DI1_PIN4 0x10000 /* HSYNC */
MX53_PAD_PATA_DA_1__GPIO7_7 0x10000 /* LCD_BLT_EN */
MX53_PAD_PATA_DA_2__GPIO7_8 0x10000 /* LCD_RESET */
MX53_PAD_PATA_DATA5__GPIO2_5 0x10000 /* LCD_POWER */
MX53_PAD_PATA_DATA6__GPIO2_6 0x10000 /* PMIC_INT */
MX53_PAD_PATA_DATA14__GPIO2_14 0x10000 /* CSI_RST */
MX53_PAD_PATA_DATA15__GPIO2_15 0x10000 /* CSI_PWDN */
MX53_PAD_GPIO_0__GPIO1_0 0x10000 /* SYSTEM_DOWN */
MX53_PAD_GPIO_3__GPIO1_3 0x10000
MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000 /* LCD_BLT_EN */
MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000 /* LCD_RESET */
MX53_PAD_PATA_DATA5__GPIO2_5 0x80000000 /* LCD_POWER */
MX53_PAD_PATA_DATA6__GPIO2_6 0x80000000 /* PMIC_INT */
MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000 /* CSI_RST */
MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000 /* CSI_PWDN */
MX53_PAD_GPIO_19__GPIO4_5 0x80000000 /* #SYSTEM_DOWN */
MX53_PAD_GPIO_3__GPIO1_3 0x80000000
MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 /* #PHY_RESET */
MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000 /* LCD_CONTRAST */
>;
};
};
@ -149,7 +160,7 @@
reg = <0x8>;
fsl,mc13xxx-uses-rtc;
interrupt-parent = <&gpio2>;
interrupts = <6 8>; /* PDATA_DATA6, low active */
interrupts = <6 4>; /* PATA_DATA6, active high */
};
sensor1: lm75@48 {

122
arch/arm/boot/dts/imx53-tx53.dtsi Normal file
View File

@ -0,0 +1,122 @@
/*
* Copyright 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/include/ "imx53.dtsi"
/ {
model = "Ka-Ro TX53";
compatible = "karo,tx53", "fsl,imx53";
memory {
reg = <0x70000000 0x40000000>; /* Up to 1GiB */
};
regulators {
compatible = "simple-bus";
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1_2>;
status = "disabled";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2_1>;
status = "disabled";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_2>;
status = "disabled";
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1_2>;
status = "disabled";
};
&esdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc2_1>;
status = "disabled";
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
status = "disabled";
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3_2>;
status = "disabled";
};
&owire {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_owire_1>;
status = "disabled";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2_1>;
status = "disabled";
};
&ssi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_1>;
status = "disabled";
};
&ssi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_2>;
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_2>,
<&pinctrl_uart1_3>;
fsl,uart-has-rtscts;
status = "disabled";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_2>;
fsl,uart-has-rtscts;
status = "disabled";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3_1>;
fsl,uart-has-rtscts;
status = "disabled";
};

297
arch/arm/boot/dts/imx53.dtsi
View File

@ -27,6 +27,9 @@
gpio4 = &gpio5;
gpio5 = &gpio6;
gpio6 = &gpio7;
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
};
tzic: tz-interrupt-controller@0fffc000 {
@ -163,10 +166,27 @@
};
};
usbphy0: usbphy@0 {
compatible = "usb-nop-xceiv";
clocks = <&clks 124>;
clock-names = "main_clk";
status = "okay";
};
usbphy1: usbphy@1 {
compatible = "usb-nop-xceiv";
clocks = <&clks 125>;
clock-names = "main_clk";
status = "okay";
};
usbotg: usb@53f80000 {
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80000 0x0200>;
interrupts = <18>;
clocks = <&clks 108>;
fsl,usbmisc = <&usbmisc 0>;
fsl,usbphy = <&usbphy0>;
status = "disabled";
};
@ -174,6 +194,9 @@
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80200 0x0200>;
interrupts = <14>;
clocks = <&clks 108>;
fsl,usbmisc = <&usbmisc 1>;
fsl,usbphy = <&usbphy1>;
status = "disabled";
};
@ -181,6 +204,8 @@
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80400 0x0200>;
interrupts = <16>;
clocks = <&clks 108>;
fsl,usbmisc = <&usbmisc 2>;
status = "disabled";
};
@ -188,9 +213,18 @@
compatible = "fsl,imx53-usb", "fsl,imx27-usb";
reg = <0x53f80600 0x0200>;
interrupts = <17>;
clocks = <&clks 108>;
fsl,usbmisc = <&usbmisc 3>;
status = "disabled";
};
usbmisc: usbmisc@53f80800 {
#index-cells = <1>;
compatible = "fsl,imx53-usbmisc";
reg = <0x53f80800 0x200>;
clocks = <&clks 108>;
};
gpio1: gpio@53f84000 {
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
reg = <0x53f84000 0x4000>;
@ -267,6 +301,24 @@
MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
>;
};
pinctrl_audmux_2: audmuxgrp-2 {
fsl,pins = <
MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x80000000
MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x80000000
MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x80000000
MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x80000000
>;
};
pinctrl_audmux_3: audmuxgrp-3 {
fsl,pins = <
MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC 0x80000000
MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD 0x80000000
MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS 0x80000000
MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD 0x80000000
>;
};
};
fec {
@ -284,6 +336,29 @@
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
>;
};
pinctrl_fec_2: fecgrp-2 {
fsl,pins = <
MX53_PAD_FEC_MDC__FEC_MDC 0x80000000
MX53_PAD_FEC_MDIO__FEC_MDIO 0x80000000
MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x80000000
MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x80000000
MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x80000000
MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x80000000
MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x80000000
MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x80000000
MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x80000000
MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x80000000
MX53_PAD_KEY_ROW1__FEC_COL 0x80000000
MX53_PAD_KEY_COL3__FEC_CRS 0x80000000
MX53_PAD_KEY_COL2__FEC_RDATA_2 0x80000000
MX53_PAD_KEY_COL0__FEC_RDATA_3 0x80000000
MX53_PAD_KEY_COL1__FEC_RX_CLK 0x80000000
MX53_PAD_KEY_ROW2__FEC_TDATA_2 0x80000000
MX53_PAD_GPIO_19__FEC_TDATA_3 0x80000000
MX53_PAD_KEY_ROW0__FEC_TX_ER 0x80000000
>;
};
};
csi {
@ -312,6 +387,22 @@
MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
>;
};
pinctrl_csi_2: csigrp-2 {
fsl,pins = <
MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC 0x1d5
MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC 0x1d5
MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK 0x1d5
MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 0x1d5
MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 0x1d5
MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 0x1d5
MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 0x1d5
MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 0x1d5
MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 0x1d5
MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 0x1d5
MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 0x1d5
>;
};
};
cspi {
@ -322,6 +413,14 @@
MX53_PAD_SD1_CLK__CSPI_SCLK 0x1d5
>;
};
pinctrl_cspi_2: cspigrp-2 {
fsl,pins = <
MX53_PAD_EIM_D22__CSPI_MISO 0x1d5
MX53_PAD_EIM_D28__CSPI_MOSI 0x1d5
MX53_PAD_EIM_D21__CSPI_SCLK 0x1d5
>;
};
};
ecspi1 {
@ -332,6 +431,27 @@
MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
>;
};
pinctrl_ecspi1_2: ecspi1grp-2 {
fsl,pins = <
MX53_PAD_GPIO_19__ECSPI1_RDY 0x80000000
MX53_PAD_EIM_EB2__ECSPI1_SS0 0x80000000
MX53_PAD_EIM_D16__ECSPI1_SCLK 0x80000000
MX53_PAD_EIM_D17__ECSPI1_MISO 0x80000000
MX53_PAD_EIM_D18__ECSPI1_MOSI 0x80000000
MX53_PAD_EIM_D19__ECSPI1_SS1 0x80000000
>;
};
};
ecspi2 {
pinctrl_ecspi2_1: ecspi2grp-1 {
fsl,pins = <
MX53_PAD_EIM_OE__ECSPI2_MISO 0x80000000
MX53_PAD_EIM_CS1__ECSPI2_MOSI 0x80000000
MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x80000000
>;
};
};
esdhc1 {
@ -406,6 +526,13 @@
MX53_PAD_KEY_ROW2__CAN1_RXCAN 0x80000000
>;
};
pinctrl_can1_3: can1grp-3 {
fsl,pins = <
MX53_PAD_GPIO_7__CAN1_TXCAN 0x80000000
MX53_PAD_GPIO_8__CAN1_RXCAN 0x80000000
>;
};
};
can2 {
@ -424,6 +551,13 @@
MX53_PAD_CSI0_DAT9__I2C1_SCL 0xc0000000
>;
};
pinctrl_i2c1_2: i2c1grp-2 {
fsl,pins = <
MX53_PAD_EIM_D21__I2C1_SCL 0xc0000000
MX53_PAD_EIM_D28__I2C1_SDA 0xc0000000
>;
};
};
i2c2 {
@ -433,6 +567,13 @@
MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
>;
};
pinctrl_i2c2_2: i2c2grp-2 {
fsl,pins = <
MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
>;
};
};
i2c3 {
@ -444,6 +585,119 @@
};
};
ipu_disp0 {
pinctrl_ipu_disp0_1: ipudisp0grp-1 {
fsl,pins = <
MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
>;
};
};
ipu_disp1 {
pinctrl_ipu_disp1_1: ipudisp1grp-1 {
fsl,pins = <
MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0 0x5
MX53_PAD_EIM_DA8__IPU_DISP1_DAT_1 0x5
MX53_PAD_EIM_DA7__IPU_DISP1_DAT_2 0x5
MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 0x5
MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 0x5
MX53_PAD_EIM_DA4__IPU_DISP1_DAT_5 0x5
MX53_PAD_EIM_DA3__IPU_DISP1_DAT_6 0x5
MX53_PAD_EIM_DA2__IPU_DISP1_DAT_7 0x5
MX53_PAD_EIM_DA1__IPU_DISP1_DAT_8 0x5
MX53_PAD_EIM_DA0__IPU_DISP1_DAT_9 0x5
MX53_PAD_EIM_EB1__IPU_DISP1_DAT_10 0x5
MX53_PAD_EIM_EB0__IPU_DISP1_DAT_11 0x5
MX53_PAD_EIM_A17__IPU_DISP1_DAT_12 0x5
MX53_PAD_EIM_A18__IPU_DISP1_DAT_13 0x5
MX53_PAD_EIM_A19__IPU_DISP1_DAT_14 0x5
MX53_PAD_EIM_A20__IPU_DISP1_DAT_15 0x5
MX53_PAD_EIM_A21__IPU_DISP1_DAT_16 0x5
MX53_PAD_EIM_A22__IPU_DISP1_DAT_17 0x5
MX53_PAD_EIM_A23__IPU_DISP1_DAT_18 0x5
MX53_PAD_EIM_A24__IPU_DISP1_DAT_19 0x5
MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 0x5
MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 0x5
MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 0x5
MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 0x5
MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x5
MX53_PAD_EIM_DA13__IPU_DI1_D0_CS 0x5
MX53_PAD_EIM_DA14__IPU_DI1_D1_CS 0x5
MX53_PAD_EIM_DA15__IPU_DI1_PIN1 0x5
MX53_PAD_EIM_DA11__IPU_DI1_PIN2 0x5
MX53_PAD_EIM_DA12__IPU_DI1_PIN3 0x5
MX53_PAD_EIM_A25__IPU_DI1_PIN12 0x5
MX53_PAD_EIM_DA10__IPU_DI1_PIN15 0x5
>;
};
};
ipu_disp2 {
pinctrl_ipu_disp2_1: ipudisp2grp-1 {
fsl,pins = <
MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000
MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000
MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000
MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000
MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1 0x80000000
MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2 0x80000000
MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3 0x80000000
MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK 0x80000000
>;
};
};
nand {
pinctrl_nand_1: nandgrp-1 {
fsl,pins = <
MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
>;
};
};
owire {
pinctrl_owire_1: owiregrp-1 {
fsl,pins = <
@ -452,6 +706,22 @@
};
};
pwm1 {
pinctrl_pwm1_1: pwm1grp-1 {
fsl,pins = <
MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
>;
};
};
pwm2 {
pinctrl_pwm2_1: pwm2grp-1 {
fsl,pins = <
MX53_PAD_GPIO_1__PWM2_PWMO 0x80000000
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
@ -466,6 +736,13 @@
MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1c5
>;
};
pinctrl_uart1_3: uart1grp-3 {
fsl,pins = <
MX53_PAD_PATA_RESET_B__UART1_CTS 0x1c5
MX53_PAD_PATA_IORDY__UART1_RTS 0x1c5
>;
};
};
uart2 {
@ -475,6 +752,15 @@
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
>;
};
pinctrl_uart2_2: uart2grp-2 {
fsl,pins = <
MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1c5
MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1c5
MX53_PAD_PATA_DIOR__UART2_RTS 0x1c5
MX53_PAD_PATA_INTRQ__UART2_CTS 0x1c5
>;
};
};
uart3 {
@ -513,7 +799,6 @@
>;
};
};
};
gpr: iomuxc-gpr@53fa8000 {
@ -781,6 +1066,16 @@
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
tve: tve@63ff0000 {
compatible = "fsl,imx53-tve";
reg = <0x63ff0000 0x1000>;
interrupts = <92>;
clocks = <&clks 69>, <&clks 116>;
clock-names = "tve", "di_sel";
crtcs = <&ipu 1>;
status = "disabled";
};
};
};
};

8
arch/arm/boot/dts/imx6dl-sabreauto.dts
View File

@ -28,4 +28,12 @@
>;
};
};
ecspi1 {
pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
fsl,pins = <
MX6DL_PAD_EIM_D19__GPIO3_IO19 0x80000000
>;
};
};
};

1
arch/arm/boot/dts/imx6dl-sabresd.dts
View File

@ -29,6 +29,7 @@
MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
MX6DL_PAD_GPIO_0__CCM_CLKO1 0x130b0
>;
};
};

112
arch/arm/boot/dts/imx6dl.dtsi
View File

@ -37,6 +37,27 @@
compatible = "fsl,imx6dl-iomuxc";
reg = <0x020e0000 0x4000>;
audmux {
pinctrl_audmux_2: audmux-2 {
fsl,pins = <
MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
>;
};
};
ecspi1 {
pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
>;
};
};
enet {
pinctrl_enet_1: enetgrp-1 {
fsl,pins = <
@ -80,6 +101,39 @@
};
};
gpmi-nand {
pinctrl_gpmi_nand_1: gpmi-nand-1 {
fsl,pins = <
MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1
>;
};
};
i2c1 {
pinctrl_i2c1_2: i2c1grp-2 {
fsl,pins = <
MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
@ -151,6 +205,64 @@
};
};
weim {
pinctrl_weim_cs0_1: weim_cs0grp-1 {
fsl,pins = <
MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
>;
};
pinctrl_weim_nor_1: weim_norgrp-1 {
fsl,pins = <
MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1
MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1
MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
/* data */
MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
/* address */
MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1
MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1
MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1
MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1
MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1
MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1
MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1
MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1
MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1
MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1
MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1
MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1
MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1
MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1
MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1
MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1
>;
};
};
};

34
arch/arm/boot/dts/imx6q-phytec-pbab01.dts Normal file
View File

@ -0,0 +1,34 @@
/*
* Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include "imx6q-phytec-pfla02.dtsi"
/ {
model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board";
compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q";
};
&fec {
status = "okay";
};
&uart4 {
status = "okay";
};
&usdhc2 {
status = "okay";
};
&usdhc3 {
status = "okay";
};

74
arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi Normal file
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@ -0,0 +1,74 @@
/*
* Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include "imx6q.dtsi"
/ {
model = "Phytec phyFLEX-i.MX6 Ouad";
compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
memory {
reg = <0x10000000 0x80000000>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000
>;
};
};
pfla02 {
pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {
fsl,pins = <
MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
>;
};
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_3>;
phy-mode = "rgmii";
phy-reset-gpios = <&gpio3 23 0>;
status = "disabled";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4_1>;
status = "disabled";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_2>;
cd-gpios = <&gpio1 4 0>;
wp-gpios = <&gpio1 2 0>;
status = "disabled";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_2
&pinctrl_usdhc3_pfla02>;
cd-gpios = <&gpio1 27 0>;
wp-gpios = <&gpio1 29 0>;
status = "disabled";
};

8
arch/arm/boot/dts/imx6q-sabreauto.dts
View File

@ -32,4 +32,12 @@
>;
};
};
ecspi1 {
pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
fsl,pins = <
MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000
>;
};
};
};

1
arch/arm/boot/dts/imx6q-sabresd.dts
View File

@ -33,6 +33,7 @@
MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000
MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000
MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000
MX6Q_PAD_GPIO_0__CCM_CLKO1 0x130b0
>;
};
};

100
arch/arm/boot/dts/imx6q.dtsi
View File

@ -161,6 +161,27 @@
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
>;
};
pinctrl_enet_3: enetgrp-3 {
fsl,pins = <
MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
>;
};
};
gpmi-nand {
@ -172,8 +193,6 @@
MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
@ -196,6 +215,13 @@
MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
>;
};
pinctrl_i2c1_2: i2c1grp-2 {
fsl,pins = <
MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
>;
};
};
i2c2 {
@ -272,6 +298,17 @@
MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
>;
};
pinctrl_usdhc2_2: usdhc2grp-2 {
fsl,pins = <
MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
};
usdhc3 {
@ -329,6 +366,65 @@
>;
};
};
weim {
pinctrl_weim_cs0_1: weim_cs0grp-1 {
fsl,pins = <
MX6Q_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
>;
};
pinctrl_weim_nor_1: weimnorgrp-1 {
fsl,pins = <
MX6Q_PAD_EIM_OE__EIM_OE_B 0xb0b1
MX6Q_PAD_EIM_RW__EIM_RW 0xb0b1
MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
/* data */
MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0
MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0
MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0
MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0
MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0
MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0
MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0
MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0
MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0
MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0
MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0
MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0
MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0
MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0
MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0
MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0
/* address */
MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1
MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1
MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1
MX6Q_PAD_EIM_DA12__EIM_AD12 0xb0b1
MX6Q_PAD_EIM_DA11__EIM_AD11 0xb0b1
MX6Q_PAD_EIM_DA10__EIM_AD10 0xb0b1
MX6Q_PAD_EIM_DA9__EIM_AD09 0xb0b1
MX6Q_PAD_EIM_DA8__EIM_AD08 0xb0b1
MX6Q_PAD_EIM_DA7__EIM_AD07 0xb0b1
MX6Q_PAD_EIM_DA6__EIM_AD06 0xb0b1
MX6Q_PAD_EIM_DA5__EIM_AD05 0xb0b1
MX6Q_PAD_EIM_DA4__EIM_AD04 0xb0b1
MX6Q_PAD_EIM_DA3__EIM_AD03 0xb0b1
MX6Q_PAD_EIM_DA2__EIM_AD02 0xb0b1
MX6Q_PAD_EIM_DA1__EIM_AD01 0xb0b1
MX6Q_PAD_EIM_DA0__EIM_AD00 0xb0b1
>;
};
};
};
};

41
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
View File

@ -16,6 +16,22 @@
};
};
&ecspi1 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1_1 &pinctrl_ecspi1_sabreauto>;
status = "disabled"; /* pin conflict with WEIM NOR */
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p32";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_2>;
@ -23,6 +39,12 @@
status = "okay";
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand_1>;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4_1>;
@ -36,3 +58,22 @@
wp-gpios = <&gpio1 13 0>;
status = "okay";
};
&weim {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_weim_nor_1 &pinctrl_weim_cs0_1>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x08000000>;
status = "disabled"; /* pin conflict with SPI NOR */
nor@0,0 {
compatible = "cfi-flash";
reg = <0 0 0x02000000>;
#address-cells = <1>;
#size-cells = <1>;
bank-width = <2>;
fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
0x0000c000 0x1404a38e 0x00000000>;
};
};

66
arch/arm/boot/dts/imx6qdl-sabresd.dtsi
View File

@ -26,6 +26,13 @@
gpio = <&gpio3 22 0>;
enable-active-high;
};
reg_audio: wm8962_supply {
compatible = "regulator-fixed";
regulator-name = "wm8962-supply";
gpio = <&gpio4 10 0>;
enable-active-high;
};
};
gpio-keys {
@ -43,6 +50,31 @@
linux,code = <114>; /* KEY_VOLUMEDOWN */
};
};
sound {
compatible = "fsl,imx6q-sabresd-wm8962",
"fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"MICBIAS", "AMIC",
"IN3R", "MICBIAS",
"DMIC", "MICBIAS",
"DMICDAT", "DMIC";
mux-int-port = <2>;
mux-ext-port = <3>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux_2>;
status = "okay";
};
&fec {
@ -52,6 +84,40 @@
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_2>;
status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks 169>;
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
PLLVDD-supply = <&reg_audio>;
SPKVDD1-supply = <&reg_audio>;
SPKVDD2-supply = <&reg_audio>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0013 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x8014 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
};
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;

13
arch/arm/boot/dts/imx6qdl.dtsi
View File

@ -106,6 +106,8 @@
interrupts = <0 92 0x04>;
cache-unified;
cache-level = <2>;
arm,tag-latency = <4 2 3>;
arm,data-latency = <4 2 3>;
};
pmu {
@ -638,7 +640,7 @@
status = "disabled";
};
usbmisc: usbmisc: usbmisc@02184800 {
usbmisc: usbmisc@02184800 {
#index-cells = <1>;
compatible = "fsl,imx6q-usbmisc";
reg = <0x02184800 0x200>;
@ -742,9 +744,11 @@
reg = <0x021b4000 0x4000>;
};
weim@021b8000 {
weim: weim@021b8000 {
compatible = "fsl,imx6q-weim";
reg = <0x021b8000 0x4000>;
interrupts = <0 14 0x04>;
clocks = <&clks 196>;
};
ocotp@021bc000 {
@ -752,11 +756,6 @@
reg = <0x021bc000 0x4000>;
};
ocotp@021c0000 {
reg = <0x021c0000 0x4000>;
interrupts = <0 21 0x04>;
};
tzasc@021d0000 { /* TZASC1 */
reg = <0x021d0000 0x4000>;
interrupts = <0 108 0x04>;

74
arch/arm/boot/dts/imx6sl-evk.dts Normal file
View File

@ -0,0 +1,74 @@
/*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include "imx6sl.dtsi"
/ {
model = "Freescale i.MX6 SoloLite EVK Board";
compatible = "fsl,imx6sl-evk", "fsl,imx6sl";
memory {
reg = <0x80000000 0x40000000>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec_1>;
phy-mode = "rmii";
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
hog {
pinctrl_hog: hoggrp {
fsl,pins = <
MX6SL_PAD_KEY_ROW7__GPIO4_IO07 0x17059
MX6SL_PAD_KEY_COL7__GPIO4_IO06 0x17059
MX6SL_PAD_SD2_DAT7__GPIO5_IO00 0x17059
MX6SL_PAD_SD2_DAT6__GPIO4_IO29 0x17059
MX6SL_PAD_REF_CLK_32K__GPIO3_IO22 0x17059
>;
};
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1_1>;
bus-width = <8>;
cd-gpios = <&gpio4 7 0>;
wp-gpios = <&gpio4 6 0>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_1>;
cd-gpios = <&gpio5 0 0>;
wp-gpios = <&gpio4 29 0>;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc3_1>;
cd-gpios = <&gpio3 22 0>;
status = "okay";
};

779
arch/arm/boot/dts/imx6sl.dtsi Normal file
View File

@ -0,0 +1,779 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include "skeleton.dtsi"
#include "imx6sl-pinfunc.h"
#include <dt-bindings/clock/imx6sl-clock.h>
/ {
aliases {
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
};
};
intc: interrupt-controller@00a01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
ckil {
compatible = "fixed-clock";
clock-frequency = <32768>;
};
osc {
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
ranges;
L2: l2-cache@00a02000 {
compatible = "arm,pl310-cache";
reg = <0x00a02000 0x1000>;
interrupts = <0 92 0x04>;
cache-unified;
cache-level = <2>;
arm,tag-latency = <4 2 3>;
arm,data-latency = <4 2 3>;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 94 0x04>;
};
aips1: aips-bus@02000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x100000>;
ranges;
spba: spba-bus@02000000 {
compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02000000 0x40000>;
ranges;
spdif: spdif@02004000 {
reg = <0x02004000 0x4000>;
interrupts = <0 52 0x04>;
};
ecspi1: ecspi@02008000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
reg = <0x02008000 0x4000>;
interrupts = <0 31 0x04>;
clocks = <&clks IMX6SL_CLK_ECSPI1>,
<&clks IMX6SL_CLK_ECSPI1>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi2: ecspi@0200c000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
reg = <0x0200c000 0x4000>;
interrupts = <0 32 0x04>;
clocks = <&clks IMX6SL_CLK_ECSPI2>,
<&clks IMX6SL_CLK_ECSPI2>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi3: ecspi@02010000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
reg = <0x02010000 0x4000>;
interrupts = <0 33 0x04>;
clocks = <&clks IMX6SL_CLK_ECSPI3>,
<&clks IMX6SL_CLK_ECSPI3>;
clock-names = "ipg", "per";
status = "disabled";
};
ecspi4: ecspi@02014000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
reg = <0x02014000 0x4000>;
interrupts = <0 34 0x04>;
clocks = <&clks IMX6SL_CLK_ECSPI4>,
<&clks IMX6SL_CLK_ECSPI4>;
clock-names = "ipg", "per";
status = "disabled";
};
uart5: serial@02018000 {
compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
reg = <0x02018000 0x4000>;
interrupts = <0 30 0x04>;
clocks = <&clks IMX6SL_CLK_UART>,
<&clks IMX6SL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
status = "disabled";
};
uart1: serial@02020000 {
compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
reg = <0x02020000 0x4000>;
interrupts = <0 26 0x04>;
clocks = <&clks IMX6SL_CLK_UART>,
<&clks IMX6SL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
status = "disabled";
};
uart2: serial@02024000 {
compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
reg = <0x02024000 0x4000>;
interrupts = <0 27 0x04>;
clocks = <&clks IMX6SL_CLK_UART>,
<&clks IMX6SL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
status = "disabled";
};
ssi1: ssi@02028000 {
compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
reg = <0x02028000 0x4000>;
interrupts = <0 46 0x04>;
clocks = <&clks IMX6SL_CLK_SSI1>;
fsl,fifo-depth = <15>;
status = "disabled";
};
ssi2: ssi@0202c000 {
compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
reg = <0x0202c000 0x4000>;
interrupts = <0 47 0x04>;
clocks = <&clks IMX6SL_CLK_SSI2>;
fsl,fifo-depth = <15>;
status = "disabled";
};
ssi3: ssi@02030000 {
compatible = "fsl,imx6sl-ssi","fsl,imx21-ssi";
reg = <0x02030000 0x4000>;
interrupts = <0 48 0x04>;
clocks = <&clks IMX6SL_CLK_SSI3>;
fsl,fifo-depth = <15>;
status = "disabled";
};
uart3: serial@02034000 {
compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
reg = <0x02034000 0x4000>;
interrupts = <0 28 0x04>;
clocks = <&clks IMX6SL_CLK_UART>,
<&clks IMX6SL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
status = "disabled";
};
uart4: serial@02038000 {
compatible = "fsl,imx6sl-uart", "fsl,imx21-uart";
reg = <0x02038000 0x4000>;
interrupts = <0 29 0x04>;
clocks = <&clks IMX6SL_CLK_UART>,
<&clks IMX6SL_CLK_UART_SERIAL>;
clock-names = "ipg", "per";
status = "disabled";
};
};
pwm1: pwm@02080000 {
#pwm-cells = <2>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x4000>;
interrupts = <0 83 0x04>;
clocks = <&clks IMX6SL_CLK_PWM1>,
<&clks IMX6SL_CLK_PWM1>;
clock-names = "ipg", "per";
};
pwm2: pwm@02084000 {
#pwm-cells = <2>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <0 84 0x04>;
clocks = <&clks IMX6SL_CLK_PWM2>,
<&clks IMX6SL_CLK_PWM2>;
clock-names = "ipg", "per";
};
pwm3: pwm@02088000 {
#pwm-cells = <2>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x4000>;
interrupts = <0 85 0x04>;
clocks = <&clks IMX6SL_CLK_PWM3>,
<&clks IMX6SL_CLK_PWM3>;
clock-names = "ipg", "per";
};
pwm4: pwm@0208c000 {
#pwm-cells = <2>;
compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <0 86 0x04>;
clocks = <&clks IMX6SL_CLK_PWM4>,
<&clks IMX6SL_CLK_PWM4>;
clock-names = "ipg", "per";
};
gpt: gpt@02098000 {
compatible = "fsl,imx6sl-gpt";
reg = <0x02098000 0x4000>;
interrupts = <0 55 0x04>;
clocks = <&clks IMX6SL_CLK_GPT>,
<&clks IMX6SL_CLK_GPT_SERIAL>;
clock-names = "ipg", "per";
};
gpio1: gpio@0209c000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x0209c000 0x4000>;
interrupts = <0 66 0x04 0 67 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio2: gpio@020a0000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x020a0000 0x4000>;
interrupts = <0 68 0x04 0 69 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio3: gpio@020a4000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x020a4000 0x4000>;
interrupts = <0 70 0x04 0 71 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio4: gpio@020a8000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x020a8000 0x4000>;
interrupts = <0 72 0x04 0 73 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
gpio5: gpio@020ac000 {
compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
reg = <0x020ac000 0x4000>;
interrupts = <0 74 0x04 0 75 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
kpp: kpp@020b8000 {
reg = <0x020b8000 0x4000>;
interrupts = <0 82 0x04>;
};
wdog1: wdog@020bc000 {
compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
reg = <0x020bc000 0x4000>;
interrupts = <0 80 0x04>;
clocks = <&clks IMX6SL_CLK_DUMMY>;
};
wdog2: wdog@020c0000 {
compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
reg = <0x020c0000 0x4000>;
interrupts = <0 81 0x04>;
clocks = <&clks IMX6SL_CLK_DUMMY>;
status = "disabled";
};
clks: ccm@020c4000 {
compatible = "fsl,imx6sl-ccm";
reg = <0x020c4000 0x4000>;
interrupts = <0 87 0x04 0 88 0x04>;
#clock-cells = <1>;
};
anatop: anatop@020c8000 {
compatible = "fsl,imx6sl-anatop", "syscon", "simple-bus";
reg = <0x020c8000 0x1000>;
interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
regulator-1p1@110 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd1p1";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1375000>;
regulator-always-on;
anatop-reg-offset = <0x110>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <4>;
anatop-min-voltage = <800000>;
anatop-max-voltage = <1375000>;
};
regulator-3p0@120 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd3p0";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3150000>;
regulator-always-on;
anatop-reg-offset = <0x120>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2625000>;
anatop-max-voltage = <3400000>;
};
regulator-2p5@130 {
compatible = "fsl,anatop-regulator";
regulator-name = "vdd2p5";
regulator-min-microvolt = <2100000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
anatop-reg-offset = <0x130>;
anatop-vol-bit-shift = <8>;
anatop-vol-bit-width = <5>;
anatop-min-bit-val = <0>;
anatop-min-voltage = <2100000>;
anatop-max-voltage = <2850000>;
};
reg_arm: regulator-vddcore@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "cpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <0>;
anatop-vol-bit-width = <5>;
anatop-delay-reg-offset = <0x170>;
anatop-delay-bit-shift = <24>;
anatop-delay-bit-width = <2>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
reg_pu: regulator-vddpu@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <9>;
anatop-vol-bit-width = <5>;
anatop-delay-reg-offset = <0x170>;
anatop-delay-bit-shift = <26>;
anatop-delay-bit-width = <2>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
reg_soc: regulator-vddsoc@140 {
compatible = "fsl,anatop-regulator";
regulator-name = "vddsoc";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <18>;
anatop-vol-bit-width = <5>;
anatop-delay-reg-offset = <0x170>;
anatop-delay-bit-shift = <28>;
anatop-delay-bit-width = <2>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1450000>;
};
};
usbphy1: usbphy@020c9000 {
compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
reg = <0x020c9000 0x1000>;
interrupts = <0 44 0x04>;
clocks = <&clks IMX6SL_CLK_USBPHY1>;
};
usbphy2: usbphy@020ca000 {
compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
reg = <0x020ca000 0x1000>;
interrupts = <0 45 0x04>;
clocks = <&clks IMX6SL_CLK_USBPHY2>;
};
snvs@020cc000 {
compatible = "fsl,sec-v4.0-mon", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x020cc000 0x4000>;
snvs-rtc-lp@34 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
reg = <0x34 0x58>;
interrupts = <0 19 0x04 0 20 0x04>;
};
};
epit1: epit@020d0000 {
reg = <0x020d0000 0x4000>;
interrupts = <0 56 0x04>;
};
epit2: epit@020d4000 {
reg = <0x020d4000 0x4000>;
interrupts = <0 57 0x04>;
};
src: src@020d8000 {
compatible = "fsl,imx6sl-src", "fsl,imx51-src";
reg = <0x020d8000 0x4000>;
interrupts = <0 91 0x04 0 96 0x04>;
#reset-cells = <1>;
};
gpc: gpc@020dc000 {
compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupts = <0 89 0x04>;
};
iomuxc: iomuxc@020e0000 {
compatible = "fsl,imx6sl-iomuxc";
reg = <0x020e0000 0x4000>;
fec {
pinctrl_fec_1: fecgrp-1 {
fsl,pins = <
MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp-1 {
fsl,pins = <
MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
>;
};
};
usdhc1 {
pinctrl_usdhc1_1: usdhc1grp-1 {
fsl,pins = <
MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
>;
};
};
usdhc2 {
pinctrl_usdhc2_1: usdhc2grp-1 {
fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
>;
};
};
usdhc3 {
pinctrl_usdhc3_1: usdhc3grp-1 {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
>;
};
};
};
csi: csi@020e4000 {
reg = <0x020e4000 0x4000>;
interrupts = <0 7 0x04>;
};
spdc: spdc@020e8000 {
reg = <0x020e8000 0x4000>;
interrupts = <0 6 0x04>;
};
sdma: sdma@020ec000 {
compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma";
reg = <0x020ec000 0x4000>;
interrupts = <0 2 0x04>;
clocks = <&clks IMX6SL_CLK_SDMA>,
<&clks IMX6SL_CLK_SDMA>;
clock-names = "ipg", "ahb";
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin";
};
pxp: pxp@020f0000 {
reg = <0x020f0000 0x4000>;
interrupts = <0 98 0x04>;
};
epdc: epdc@020f4000 {
reg = <0x020f4000 0x4000>;
interrupts = <0 97 0x04>;
};
lcdif: lcdif@020f8000 {
reg = <0x020f8000 0x4000>;
interrupts = <0 39 0x04>;
};
dcp: dcp@020fc000 {
reg = <0x020fc000 0x4000>;
interrupts = <0 99 0x04>;
};
};
aips2: aips-bus@02100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x02100000 0x100000>;
ranges;
usbotg1: usb@02184000 {
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
reg = <0x02184000 0x200>;
interrupts = <0 43 0x04>;
clocks = <&clks IMX6SL_CLK_USBOH3>;
fsl,usbphy = <&usbphy1>;
fsl,usbmisc = <&usbmisc 0>;
status = "disabled";
};
usbotg2: usb@02184200 {
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
reg = <0x02184200 0x200>;
interrupts = <0 40 0x04>;
clocks = <&clks IMX6SL_CLK_USBOH3>;
fsl,usbphy = <&usbphy2>;
fsl,usbmisc = <&usbmisc 1>;
status = "disabled";
};
usbh: usb@02184400 {
compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
reg = <0x02184400 0x200>;
interrupts = <0 42 0x04>;
clocks = <&clks IMX6SL_CLK_USBOH3>;
fsl,usbmisc = <&usbmisc 2>;
status = "disabled";
};
usbmisc: usbmisc@02184800 {
#index-cells = <1>;
compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
reg = <0x02184800 0x200>;
clocks = <&clks IMX6SL_CLK_USBOH3>;
};
fec: ethernet@02188000 {
compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
reg = <0x02188000 0x4000>;
interrupts = <0 114 0x04>;
clocks = <&clks IMX6SL_CLK_ENET_REF>,
<&clks IMX6SL_CLK_ENET_REF>;
clock-names = "ipg", "ahb";
status = "disabled";
};
usdhc1: usdhc@02190000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02190000 0x4000>;
interrupts = <0 22 0x04>;
clocks = <&clks IMX6SL_CLK_USDHC1>,
<&clks IMX6SL_CLK_USDHC1>,
<&clks IMX6SL_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
usdhc2: usdhc@02194000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02194000 0x4000>;
interrupts = <0 23 0x04>;
clocks = <&clks IMX6SL_CLK_USDHC2>,
<&clks IMX6SL_CLK_USDHC2>,
<&clks IMX6SL_CLK_USDHC2>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
usdhc3: usdhc@02198000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x02198000 0x4000>;
interrupts = <0 24 0x04>;
clocks = <&clks IMX6SL_CLK_USDHC3>,
<&clks IMX6SL_CLK_USDHC3>,
<&clks IMX6SL_CLK_USDHC3>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
usdhc4: usdhc@0219c000 {
compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
reg = <0x0219c000 0x4000>;
interrupts = <0 25 0x04>;
clocks = <&clks IMX6SL_CLK_USDHC4>,
<&clks IMX6SL_CLK_USDHC4>,
<&clks IMX6SL_CLK_USDHC4>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
status = "disabled";
};
i2c1: i2c@021a0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
reg = <0x021a0000 0x4000>;
interrupts = <0 36 0x04>;
clocks = <&clks IMX6SL_CLK_I2C1>;
status = "disabled";
};
i2c2: i2c@021a4000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
reg = <0x021a4000 0x4000>;
interrupts = <0 37 0x04>;
clocks = <&clks IMX6SL_CLK_I2C2>;
status = "disabled";
};
i2c3: i2c@021a8000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
reg = <0x021a8000 0x4000>;
interrupts = <0 38 0x04>;
clocks = <&clks IMX6SL_CLK_I2C3>;
status = "disabled";
};
mmdc: mmdc@021b0000 {
compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
reg = <0x021b0000 0x4000>;
};
rngb: rngb@021b4000 {
reg = <0x021b4000 0x4000>;
interrupts = <0 5 0x04>;
};
weim: weim@021b8000 {
reg = <0x021b8000 0x4000>;
interrupts = <0 14 0x04>;
};
ocotp: ocotp@021bc000 {
compatible = "fsl,imx6sl-ocotp";
reg = <0x021bc000 0x4000>;
};
audmux: audmux@021d8000 {
compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
reg = <0x021d8000 0x4000>;
status = "disabled";
};
};
};
};

810
arch/arm/boot/dts/vf610-pinfunc.h Normal file
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@ -0,0 +1,810 @@
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DTS_VF610_PINFUNC_H
#define __DTS_VF610_PINFUNC_H
/*
* The pin function ID for VF610 is a tuple of:
* <mux_reg input_reg mux_mode input_val>
*/
#define ALT0 0x0
#define ALT1 0x1
#define ALT2 0x2
#define ALT3 0x3
#define ALT4 0x4
#define ALT5 0x5
#define ALT6 0x6
#define ALT7 0x7
#define VF610_PAD_PTA6__GPIO_0 0x000 0x000 ALT0 0x0
#define VF610_PAD_PTA6__RMII_CLKOUT 0x000 0x000 ALT1 0x0
#define VF610_PAD_PTA6__RMII_CLKIN 0x000 0x2F0 ALT2 0x0
#define VF610_PAD_PTA6__DCU1_TCON11 0x000 0x000 ALT4 0x0
#define VF610_PAD_PTA6__DCU1_R2 0x000 0x000 ALT7 0x0
#define VF610_PAD_PTA8__GPIO_1 0x004 0x000 ALT0 0x0
#define VF610_PAD_PTA8__TCLK 0x004 0x000 ALT1 0x0
#define VF610_PAD_PTA8__DCU0_R0 0x004 0x000 ALT4 0x0
#define VF610_PAD_PTA8__MLB_CLK 0x004 0x354 ALT7 0x0
#define VF610_PAD_PTA9__GPIO_2 0x008 0x000 ALT0 0x0
#define VF610_PAD_PTA9__TDI 0x008 0x000 ALT1 0x0
#define VF610_PAD_PTA9__RMII_CLKOUT 0x008 0x000 ALT2 0x0
#define VF610_PAD_PTA9__RMII_CLKIN 0x008 0x2F0 ALT3 0x1
#define VF610_PAD_PTA9__DCU0_R1 0x008 0x000 ALT4 0x0
#define VF610_PAD_PTA9__WDOG_B 0x008 0x000 ALT6 0x0
#define VF610_PAD_PTA10__GPIO_3 0x00C 0x000 ALT0 0x0
#define VF610_PAD_PTA10__TDO 0x00C 0x000 ALT1 0x0
#define VF610_PAD_PTA10__EXT_AUDIO_MCLK 0x00C 0x2EC ALT2 0x0
#define VF610_PAD_PTA10__DCU0_G0 0x00C 0x000 ALT4 0x0
#define VF610_PAD_PTA10__ENET_TS_CLKIN 0x00C 0x2F4 ALT6 0x0
#define VF610_PAD_PTA10__MLB_SIGNAL 0x00C 0x35C ALT7 0x0
#define VF610_PAD_PTA11__GPIO_4 0x010 0x000 ALT0 0x0
#define VF610_PAD_PTA11__TMS 0x010 0x000 ALT1 0x0
#define VF610_PAD_PTA11__DCU0_G1 0x010 0x000 ALT4 0x0
#define VF610_PAD_PTA11__MLB_DATA 0x010 0x358 ALT7 0x0
#define VF610_PAD_PTA12__GPIO_5 0x014 0x000 ALT0 0x0
#define VF610_PAD_PTA12__TRACECK 0x014 0x000 ALT1 0x0
#define VF610_PAD_PTA12__EXT_AUDIO_MCLK 0x014 0x2EC ALT2 0x1
#define VF610_PAD_PTA12__VIU_DATA13 0x014 0x000 ALT6 0x0
#define VF610_PAD_PTA12__I2C0_SCL 0x014 0x33C ALT7 0x0
#define VF610_PAD_PTA16__GPIO_6 0x018 0x000 ALT0 0x0
#define VF610_PAD_PTA16__TRACED0 0x018 0x000 ALT1 0x0
#define VF610_PAD_PTA16__USB0_VBUS_EN 0x018 0x000 ALT2 0x0
#define VF610_PAD_PTA16__ADC1_SE0 0x018 0x000 ALT3 0x0
#define VF610_PAD_PTA16__LCD29 0x018 0x000 ALT4 0x0
#define VF610_PAD_PTA16__SAI2_TX_BCLK 0x018 0x370 ALT5 0x0
#define VF610_PAD_PTA16__VIU_DATA14 0x018 0x000 ALT6 0x0
#define VF610_PAD_PTA16__I2C0_SDA 0x018 0x340 ALT7 0x0
#define VF610_PAD_PTA17__GPIO_7 0x01C 0x000 ALT0 0x0
#define VF610_PAD_PTA17__TRACED1 0x01C 0x000 ALT1 0x0
#define VF610_PAD_PTA17__USB0_VBUS_OC 0x01C 0x000 ALT2 0x0
#define VF610_PAD_PTA17__ADC1_SE1 0x01C 0x000 ALT3 0x0
#define VF610_PAD_PTA17__LCD30 0x01C 0x000 ALT4 0x0
#define VF610_PAD_PTA17__USB0_SOF_PULSE 0x01C 0x000 ALT5 0x0
#define VF610_PAD_PTA17__VIU_DATA15 0x01C 0x000 ALT6 0x0
#define VF610_PAD_PTA17__I2C1_SCL 0x01C 0x344 ALT7 0x0
#define VF610_PAD_PTA18__GPIO_8 0x020 0x000 ALT0 0x0
#define VF610_PAD_PTA18__TRACED2 0x020 0x000 ALT1 0x0
#define VF610_PAD_PTA18__ADC0_SE0 0x020 0x000 ALT2 0x0
#define VF610_PAD_PTA18__FTM1_QD_PHA 0x020 0x334 ALT3 0x0
#define VF610_PAD_PTA18__LCD31 0x020 0x000 ALT4 0x0
#define VF610_PAD_PTA18__SAI2_TX_DATA 0x020 0x000 ALT5 0x0
#define VF610_PAD_PTA18__VIU_DATA16 0x020 0x000 ALT6 0x0
#define VF610_PAD_PTA18__I2C1_SDA 0x020 0x348 ALT7 0x0
#define VF610_PAD_PTA19__GPIO_9 0x024 0x000 ALT0 0x0
#define VF610_PAD_PTA19__TRACED3 0x024 0x000 ALT1 0x0
#define VF610_PAD_PTA19__ADC0_SE1 0x024 0x000 ALT2 0x0
#define VF610_PAD_PTA19__FTM1_QD_PHB 0x024 0x338 ALT3 0x0
#define VF610_PAD_PTA19__LCD32 0x024 0x000 ALT4 0x0
#define VF610_PAD_PTA19__SAI2_TX_SYNC 0x024 0x000 ALT5 0x0
#define VF610_PAD_PTA19__VIU_DATA17 0x024 0x000 ALT6 0x0
#define VF610_PAD_PTA19__QSPI1_A_QSCK 0x024 0x374 ALT7 0x0
#define VF610_PAD_PTA20__GPIO_10 0x028 0x000 ALT0 0x0
#define VF610_PAD_PTA20__TRACED4 0x028 0x000 ALT1 0x0
#define VF610_PAD_PTA20__LCD33 0x028 0x000 ALT4 0x0
#define VF610_PAD_PTA20__UART3_TX 0x028 0x394 ALT6 0x0
#define VF610_PAD_PTA20__DCU1_HSYNC 0x028 0x000 ALT7 0x0
#define VF610_PAD_PTA21__GPIO_11 0x02C 0x000 ALT0 0x0
#define VF610_PAD_PTA21__TRACED5 0x02C 0x000 ALT1 0x0
#define VF610_PAD_PTA21__SAI2_RX_BCLK 0x02C 0x364 ALT5 0x0
#define VF610_PAD_PTA21__UART3_RX 0x02C 0x390 ALT6 0x0
#define VF610_PAD_PTA21__DCU1_VSYNC 0x02C 0x000 ALT7 0x0
#define VF610_PAD_PTA22__GPIO_12 0x030 0x000 ALT0 0x0
#define VF610_PAD_PTA22__TRACED6 0x030 0x000 ALT1 0x0
#define VF610_PAD_PTA22__SAI2_RX_DATA 0x030 0x368 ALT5 0x0
#define VF610_PAD_PTA22__I2C2_SCL 0x030 0x34C ALT6 0x0
#define VF610_PAD_PTA22__DCU1_TAG 0x030 0x000 ALT7 0x0
#define VF610_PAD_PTA23__GPIO_13 0x034 0x000 ALT0 0x0
#define VF610_PAD_PTA23__TRACED7 0x034 0x000 ALT1 0x0
#define VF610_PAD_PTA23__SAI2_RX_SYNC 0x034 0x36C ALT5 0x0
#define VF610_PAD_PTA23__I2C2_SDA 0x034 0x350 ALT6 0x0
#define VF610_PAD_PTA23__DCU1_DE 0x034 0x000 ALT7 0x0
#define VF610_PAD_PTA24__GPIO_14 0x038 0x000 ALT0 0x0
#define VF610_PAD_PTA24__TRACED8 0x038 0x000 ALT1 0x0
#define VF610_PAD_PTA24__USB1_VBUS_EN 0x038 0x000 ALT2 0x0
#define VF610_PAD_PTA24__ESDHC1_CLK 0x038 0x000 ALT5 0x0
#define VF610_PAD_PTA24__DCU1_TCON4 0x038 0x000 ALT6 0x0
#define VF610_PAD_PTA24__DDR_TEST_PAD_CTRL 0x038 0x000 ALT7 0x0
#define VF610_PAD_PTA25__GPIO_15 0x03C 0x000 ALT0 0x0
#define VF610_PAD_PTA25__TRACED9 0x03C 0x000 ALT1 0x0
#define VF610_PAD_PTA25__USB1_VBUS_OC 0x03C 0x000 ALT2 0x0
#define VF610_PAD_PTA25__ESDHC1_CMD 0x03C 0x000 ALT5 0x0
#define VF610_PAD_PTA25__DCU1_TCON5 0x03C 0x000 ALT6 0x0
#define VF610_PAD_PTA26__GPIO_16 0x040 0x000 ALT0 0x0
#define VF610_PAD_PTA26__TRACED10 0x040 0x000 ALT1 0x0
#define VF610_PAD_PTA26__SAI3_TX_BCLK 0x040 0x000 ALT2 0x0
#define VF610_PAD_PTA26__ESDHC1_DAT0 0x040 0x000 ALT5 0x0
#define VF610_PAD_PTA26__DCU1_TCON6 0x040 0x000 ALT6 0x0
#define VF610_PAD_PTA27__GPIO_17 0x044 0x000 ALT0 0x0
#define VF610_PAD_PTA27__TRACED11 0x044 0x000 ALT1 0x0
#define VF610_PAD_PTA27__SAI3_RX_BCLK 0x044 0x000 ALT2 0x0
#define VF610_PAD_PTA27__ESDHC1_DAT1 0x044 0x000 ALT5 0x0
#define VF610_PAD_PTA27__DCU1_TCON7 0x044 0x000 ALT6 0x0
#define VF610_PAD_PTA28__GPIO_18 0x048 0x000 ALT0 0x0
#define VF610_PAD_PTA28__TRACED12 0x048 0x000 ALT1 0x0
#define VF610_PAD_PTA28__SAI3_RX_DATA 0x048 0x000 ALT2 0x0
#define VF610_PAD_PTA28__ENET1_1588_TMR0 0x048 0x000 ALT3 0x0
#define VF610_PAD_PTA28__UART4_TX 0x048 0x000 ALT4 0x0
#define VF610_PAD_PTA28__ESDHC1_DATA2 0x048 0x000 ALT5 0x0
#define VF610_PAD_PTA28__DCU1_TCON8 0x048 0x000 ALT6 0x0
#define VF610_PAD_PTA29__GPIO_19 0x04C 0x000 ALT0 0x0
#define VF610_PAD_PTA29__TRACED13 0x04C 0x000 ALT1 0x0
#define VF610_PAD_PTA29__SAI3_TX_DATA 0x04C 0x000 ALT2 0x0
#define VF610_PAD_PTA29__ENET1_1588_TMR1 0x04C 0x000 ALT3 0x0
#define VF610_PAD_PTA29__UART4_RX 0x04C 0x000 ALT4 0x0
#define VF610_PAD_PTA29__ESDHC1_DAT3 0x04C 0x000 ALT5 0x0
#define VF610_PAD_PTA29__DCU1_TCON9 0x04C 0x000 ALT6 0x0
#define VF610_PAD_PTA30__GPIO_20 0x050 0x000 ALT0 0x0
#define VF610_PAD_PTA30__TRACED14 0x050 0x000 ALT1 0x0
#define VF610_PAD_PTA30__SAI3_RX_SYNC 0x050 0x000 ALT2 0x0
#define VF610_PAD_PTA30__ENET1_1588_TMR2 0x050 0x000 ALT3 0x0
#define VF610_PAD_PTA30__UART4_RTS 0x050 0x000 ALT4 0x0
#define VF610_PAD_PTA30__I2C3_SCL 0x050 0x000 ALT5 0x0
#define VF610_PAD_PTA30__UART3_TX 0x050 0x394 ALT7 0x1
#define VF610_PAD_PTA31__GPIO_21 0x054 0x000 ALT0 0x0
#define VF610_PAD_PTA31__TRACED15 0x054 0x000 ALT1 0x0
#define VF610_PAD_PTA31__SAI3_TX_SYNC 0x054 0x000 ALT2 0x0
#define VF610_PAD_PTA31__ENET1_1588_TMR3 0x054 0x000 ALT3 0x0
#define VF610_PAD_PTA31__UART4_CTS 0x054 0x000 ALT4 0x0
#define VF610_PAD_PTA31__I2C3_SDA 0x054 0x000 ALT5 0x0
#define VF610_PAD_PTA31__UART3_RX 0x054 0x390 ALT7 0x1
#define VF610_PAD_PTB0__GPIO_22 0x058 0x000 ALT0 0x0
#define VF610_PAD_PTB0__FTM0_CH0 0x058 0x000 ALT1 0x0
#define VF610_PAD_PTB0__ADC0_SE2 0x058 0x000 ALT2 0x0
#define VF610_PAD_PTB0__TRACE_CTL 0x058 0x000 ALT3 0x0
#define VF610_PAD_PTB0__LCD34 0x058 0x000 ALT4 0x0
#define VF610_PAD_PTB0__SAI2_RX_BCLK 0x058 0x364 ALT5 0x1
#define VF610_PAD_PTB0__VIU_DATA18 0x058 0x000 ALT6 0x0
#define VF610_PAD_PTB0__QSPI1_A_QPCS0 0x058 0x000 ALT7 0x0
#define VF610_PAD_PTB1__GPIO_23 0x05C 0x000 ALT0 0x0
#define VF610_PAD_PTB1__FTM0_CH1 0x05C 0x000 ALT1 0x0
#define VF610_PAD_PTB1__ADC0_SE3 0x05C 0x000 ALT2 0x0
#define VF610_PAD_PTB1__SRC_RCON30 0x05C 0x000 ALT3 0x0
#define VF610_PAD_PTB1__LCD35 0x05C 0x000 ALT4 0x0
#define VF610_PAD_PTB1__SAI2_RX_DATA 0x05C 0x368 ALT5 0x1
#define VF610_PAD_PTB1__VIU_DATA19 0x05C 0x000 ALT6 0x0
#define VF610_PAD_PTB1__QSPI1_A_DATA3 0x05C 0x000 ALT7 0x0
#define VF610_PAD_PTB2__GPIO_24 0x060 0x000 ALT0 0x0
#define VF610_PAD_PTB2__FTM0_CH2 0x060 0x000 ALT1 0x0
#define VF610_PAD_PTB2__ADC1_SE2 0x060 0x000 ALT2 0x0
#define VF610_PAD_PTB2__SRC_RCON31 0x060 0x000 ALT3 0x0
#define VF610_PAD_PTB2__LCD36 0x060 0x000 ALT4 0x0
#define VF610_PAD_PTB2__SAI2_RX_SYNC 0x060 0x36C ALT5 0x1
#define VF610_PAD_PTB2__VIDEO_IN0_DATA20 0x060 0x000 ALT6 0x0
#define VF610_PAD_PTB2__QSPI1_A_DATA2 0x060 0x000 ALT7 0x0
#define VF610_PAD_PTB3__GPIO_25 0x064 0x000 ALT0 0x0
#define VF610_PAD_PTB3__FTM0_CH3 0x064 0x000 ALT1 0x0
#define VF610_PAD_PTB3__ADC1_SE3 0x064 0x000 ALT2 0x0
#define VF610_PAD_PTB3__PDB_EXTRIG 0x064 0x000 ALT3 0x0
#define VF610_PAD_PTB3__LCD37 0x064 0x000 ALT4 0x0
#define VF610_PAD_PTB3__VIU_DATA21 0x064 0x000 ALT6 0x0
#define VF610_PAD_PTB3__QSPI1_A_DATA1 0x064 0x000 ALT7 0x0
#define VF610_PAD_PTB4__GPIO_26 0x068 0x000 ALT0 0x0
#define VF610_PAD_PTB4__FTM0_CH4 0x068 0x000 ALT1 0x0
#define VF610_PAD_PTB4__UART1_TX 0x068 0x380 ALT2 0x0
#define VF610_PAD_PTB4__ADC0_SE4 0x068 0x000 ALT3 0x0
#define VF610_PAD_PTB4__LCD38 0x068 0x000 ALT4 0x0
#define VF610_PAD_PTB4__VIU_FID 0x068 0x3A8 ALT5 0x0
#define VF610_PAD_PTB4__VIU_DATA22 0x068 0x000 ALT6 0x0
#define VF610_PAD_PTB4__QSPI1_A_DATA0 0x068 0x000 ALT7 0x0
#define VF610_PAD_PTB5__GPIO_27 0x06C 0x000 ALT0 0x0
#define VF610_PAD_PTB5__FTM0_CH5 0x06C 0x000 ALT1 0x0
#define VF610_PAD_PTB5__UART1_RX 0x06C 0x37C ALT2 0x0
#define VF610_PAD_PTB5__ADC1_SE4 0x06C 0x000 ALT3 0x0
#define VF610_PAD_PTB5__LCD39 0x06C 0x000 ALT4 0x0
#define VF610_PAD_PTB5__VIU_DE 0x06C 0x3A4 ALT5 0x0
#define VF610_PAD_PTB5__QSPI1_A_DQS 0x06C 0x000 ALT7 0x0
#define VF610_PAD_PTB6__GPIO_28 0x070 0x000 ALT0 0x0
#define VF610_PAD_PTB6__FTM0_CH6 0x070 0x000 ALT1 0x0
#define VF610_PAD_PTB6__UART1_RTS 0x070 0x000 ALT2 0x0
#define VF610_PAD_PTB6__QSPI0_QPCS1_A 0x070 0x000 ALT3 0x0
#define VF610_PAD_PTB6__LCD_LCD40 0x070 0x000 ALT4 0x0
#define VF610_PAD_PTB6__FB_CLKOUT 0x070 0x000 ALT5 0x0
#define VF610_PAD_PTB6__VIU_HSYNC 0x070 0x000 ALT6 0x0
#define VF610_PAD_PTB6__UART2_TX 0x070 0x38C ALT7 0x0
#define VF610_PAD_PTB7__GPIO_29 0x074 0x000 ALT0 0x0
#define VF610_PAD_PTB7__FTM0_CH7 0x074 0x000 ALT1 0x0
#define VF610_PAD_PTB7__UART1_CTS 0x074 0x378 ALT2 0x0
#define VF610_PAD_PTB7__QSPI0_B_QPCS1 0x074 0x000 ALT3 0x0
#define VF610_PAD_PTB7__LCD41 0x074 0x000 ALT4 0x0
#define VF610_PAD_PTB7__VIU_VSYNC 0x074 0x000 ALT6 0x0
#define VF610_PAD_PTB7__UART2_RX 0x074 0x388 ALT7 0x0
#define VF610_PAD_PTB8__GPIO_30 0x078 0x000 ALT0 0x0
#define VF610_PAD_PTB8__FTM1_CH0 0x078 0x32C ALT1 0x0
#define VF610_PAD_PTB8__FTM1_QD_PHA 0x078 0x334 ALT3 0x1
#define VF610_PAD_PTB8__VIU_DE 0x078 0x3A4 ALT5 0x1
#define VF610_PAD_PTB8__DCU1_R6 0x078 0x000 ALT7 0x0
#define VF610_PAD_PTB9__GPIO_31 0x07C 0x000 ALT0 0x0
#define VF610_PAD_PTB9__FTM1_CH1 0x07C 0x330 ALT1 0x0
#define VF610_PAD_PTB9__FTM1_QD_PHB 0x07C 0x338 ALT3 0x1
#define VF610_PAD_PTB9__DCU1_R7 0x07C 0x000 ALT7 0x0
#define VF610_PAD_PTB10__GPIO_32 0x080 0x000 ALT0 0x0
#define VF610_PAD_PTB10__UART0_TX 0x080 0x000 ALT1 0x0
#define VF610_PAD_PTB10__DCU0_TCON4 0x080 0x000 ALT4 0x0
#define VF610_PAD_PTB10__VIU_DE 0x080 0x3A4 ALT5 0x2
#define VF610_PAD_PTB10__CKO1 0x080 0x000 ALT6 0x0
#define VF610_PAD_PTB10__ENET_TS_CLKIN 0x080 0x2F4 ALT7 0x1
#define VF610_PAD_PTB11__GPIO_33 0x084 0x000 ALT0 0x0
#define VF610_PAD_PTB11__UART0_RX 0x084 0x000 ALT1 0x0
#define VF610_PAD_PTB11__DCU0_TCON5 0x084 0x000 ALT4 0x0
#define VF610_PAD_PTB11__SNVS_ALARM_OUT_B 0x084 0x000 ALT5 0x0
#define VF610_PAD_PTB11__CKO2 0x084 0x000 ALT6 0x0
#define VF610_PAD_PTB11_ENET0_1588_TMR0 0x084 0x304 ALT7 0x0
#define VF610_PAD_PTB12__GPIO_34 0x088 0x000 ALT0 0x0
#define VF610_PAD_PTB12__UART0_RTS 0x088 0x000 ALT1 0x0
#define VF610_PAD_PTB12__DSPI0_CS5 0x088 0x000 ALT3 0x0
#define VF610_PAD_PTB12__DCU0_TCON6 0x088 0x000 ALT4 0x0
#define VF610_PAD_PTB12__FB_AD1 0x088 0x000 ALT5 0x0
#define VF610_PAD_PTB12__NMI 0x088 0x000 ALT6 0x0
#define VF610_PAD_PTB12__ENET0_1588_TMR1 0x088 0x308 ALT7 0x0
#define VF610_PAD_PTB13__GPIO_35 0x08C 0x000 ALT0 0x0
#define VF610_PAD_PTB13__UART0_CTS 0x08C 0x000 ALT1 0x0
#define VF610_PAD_PTB13__DSPI0_CS4 0x08C 0x000 ALT3 0x0
#define VF610_PAD_PTB13__DCU0_TCON7 0x08C 0x000 ALT4 0x0
#define VF610_PAD_PTB13__FB_AD0 0x08C 0x000 ALT5 0x0
#define VF610_PAD_PTB13__TRACE_CTL 0x08C 0x000 ALT6 0x0
#define VF610_PAD_PTB14__GPIO_36 0x090 0x000 ALT0 0x0
#define VF610_PAD_PTB14__CAN0_RX 0x090 0x000 ALT1 0x0
#define VF610_PAD_PTB14__I2C0_SCL 0x090 0x33C ALT2 0x1
#define VF610_PAD_PTB14__DCU0_TCON8 0x090 0x000 ALT4 0x0
#define VF610_PAD_PTB14__DCU1_PCLK 0x090 0x000 ALT7 0x0
#define VF610_PAD_PTB15__GPIO_37 0x094 0x000 ALT0 0x0
#define VF610_PAD_PTB15__CAN0_TX 0x094 0x000 ALT1 0x0
#define VF610_PAD_PTB15__I2C0_SDA 0x094 0x340 ALT2 0x1
#define VF610_PAD_PTB15__DCU0_TCON9 0x094 0x000 ALT4 0x0
#define VF610_PAD_PTB15__VIU_PIX_CLK 0x094 0x3AC ALT7 0x0
#define VF610_PAD_PTB16__GPIO_38 0x098 0x000 ALT0 0x0
#define VF610_PAD_PTB16__CAN1_RX 0x098 0x000 ALT1 0x0
#define VF610_PAD_PTB16__I2C1_SCL 0x098 0x344 ALT2 0x1
#define VF610_PAD_PTB16__DCU0_TCON10 0x098 0x000 ALT4 0x0
#define VF610_PAD_PTB17__GPIO_39 0x09C 0x000 ALT0 0x0
#define VF610_PAD_PTB17__CAN1_TX 0x09C 0x000 ALT1 0x0
#define VF610_PAD_PTB17__I2C1_SDA 0x09C 0x348 ALT2 0x1
#define VF610_PAD_PTB17__DCU0_TCON11 0x09C 0x000 ALT4 0x0
#define VF610_PAD_PTB18__GPIO_40 0x0A0 0x000 ALT0 0x0
#define VF610_PAD_PTB18__DSPI0_CS1 0x0A0 0x000 ALT1 0x0
#define VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x0A0 0x2EC ALT2 0x2
#define VF610_PAD_PTB18__VIU_DATA9 0x0A0 0x000 ALT6 0x0
#define VF610_PAD_PTB19__GPIO_41 0x0A4 0x000 ALT0 0x0
#define VF610_PAD_PTB19__DSPI0_CS0 0x0A4 0x000 ALT1 0x0
#define VF610_PAD_PTB19__VIU_DATA10 0x0A4 0x000 ALT6 0x0
#define VF610_PAD_PTB20__GPIO_42 0x0A8 0x000 ALT0 0x0
#define VF610_PAD_PTB20__DSPI0_SIN 0x0A8 0x000 ALT1 0x0
#define VF610_PAD_PTB20__LCD42 0x0A8 0x000 ALT4 0x0
#define VF610_PAD_PTB20__VIU_DATA11 0x0A8 0x000 ALT6 0x0
#define VF610_PAD_PTB21__GPIO_43 0x0AC 0x000 ALT0 0x0
#define VF610_PAD_PTB21__DSPI0_SOUT 0x0AC 0x000 ALT1 0x0
#define VF610_PAD_PTB21__LCD43 0x0AC 0x000 ALT4 0x0
#define VF610_PAD_PTB21__VIU_DATA12 0x0AC 0x000 ALT6 0x0
#define VF610_PAD_PTB21__DCU1_PCLK 0x0AC 0x000 ALT7 0x0
#define VF610_PAD_PTB22__GPIO_44 0x0B0 0x000 ALT0 0x0
#define VF610_PAD_PTB22__DSPI0_SCK 0x0B0 0x000 ALT1 0x0
#define VF610_PAD_PTB22__VLCD 0x0B0 0x000 ALT4 0x0
#define VF610_PAD_PTB22__VIU_FID 0x0B0 0x3A8 ALT5 0x1
#define VF610_PAD_PTC0__GPIO_45 0x0B4 0x000 ALT0 0x0
#define VF610_PAD_PTC0__ENET_RMII0_MDC 0x0B4 0x000 ALT1 0x0
#define VF610_PAD_PTC0__FTM1_CH0 0x0B4 0x32C ALT2 0x1
#define VF610_PAD_PTC0__DSPI0_CS3 0x0B4 0x000 ALT3 0x0
#define VF610_PAD_PTC0__ESAI_SCKT 0x0B4 0x310 ALT4 0x0
#define VF610_PAD_PTC0__ESDHC0_CLK 0x0B4 0x000 ALT5 0x0
#define VF610_PAD_PTC0__VIU_DATA0 0x0B4 0x000 ALT6 0x0
#define VF610_PAD_PTC0__SRC_RCON18 0x0B4 0x398 ALT7 0x0
#define VF610_PAD_PTC1__GPIO_46 0x0B8 0x000 ALT0 0x0
#define VF610_PAD_PTC1__ENET_RMII0_MDIO 0x0B8 0x000 ALT1 0x0
#define VF610_PAD_PTC1__FTM1_CH1 0x0B8 0x330 ALT2 0x1
#define VF610_PAD_PTC1__DSPI0_CS2 0x0B8 0x000 ALT3 0x0
#define VF610_PAD_PTC1__ESAI_FST 0x0B8 0x30C ALT4 0x0
#define VF610_PAD_PTC1__ESDHC0_CMD 0x0B8 0x000 ALT5 0x0
#define VF610_PAD_PTC1__VIU_DATA1 0x0B8 0x000 ALT6 0x0
#define VF610_PAD_PTC1__SRC_RCON19 0x0B8 0x39C ALT7 0x0
#define VF610_PAD_PTC2__GPIO_47 0x0BC 0x000 ALT0 0x0
#define VF610_PAD_PTC2__ENET_RMII0_CRS 0x0BC 0x000 ALT1 0x0
#define VF610_PAD_PTC2__UART1_TX 0x0BC 0x380 ALT2 0x1
#define VF610_PAD_PTC2__ESAI_SDO0 0x0BC 0x314 ALT4 0x0
#define VF610_PAD_PTC2__ESDHC0_DAT0 0x0BC 0x000 ALT5 0x0
#define VF610_PAD_PTC2__VIU_DATA2 0x0BC 0x000 ALT6 0x0
#define VF610_PAD_PTC2__SRC_RCON20 0x0BC 0x3A0 ALT7 0x0
#define VF610_PAD_PTC3__GPIO_48 0x0C0 0x000 ALT0 0x0
#define VF610_PAD_PTC3__ENET_RMII0_RXD1 0x0C0 0x000 ALT1 0x0
#define VF610_PAD_PTC3__UART1_RX 0x0C0 0x37C ALT2 0x1
#define VF610_PAD_PTC3__ESAI_SDO1 0x0C0 0x318 ALT4 0x0
#define VF610_PAD_PTC3__ESDHC0_DAT1 0x0C0 0x000 ALT5 0x0
#define VF610_PAD_PTC3__VIU_DATA3 0x0C0 0x000 ALT6 0x0
#define VF610_PAD_PTC3__DCU0_R0 0x0C0 0x000 ALT7 0x0
#define VF610_PAD_PTC4__GPIO_49 0x0C4 0x000 ALT0 0x0
#define VF610_PAD_PTC4__ENET_RMII0_RXD0 0x0C4 0x000 ALT1 0x0
#define VF610_PAD_PTC4__UART1_RTS 0x0C4 0x000 ALT2 0x0
#define VF610_PAD_PTC4__DSPI1_CS1 0x0C4 0x000 ALT3 0x0
#define VF610_PAD_PTC4__ESAI_SDO2 0x0C4 0x31C ALT4 0x0
#define VF610_PAD_PTC4__ESDHC0_DAT2 0x0C4 0x000 ALT5 0x0
#define VF610_PAD_PTC4__VIU_DATA4 0x0C4 0x000 ALT6 0x0
#define VF610_PAD_PTC4__DCU0_R1 0x0C4 0x000 ALT7 0x0
#define VF610_PAD_PTC5__GPIO_50 0x0C8 0x000 ALT0 0x0
#define VF610_PAD_PTC5__ENET_RMII0_RXER 0x0C8 0x000 ALT1 0x0
#define VF610_PAD_PTC5__UART1_CTS 0x0C8 0x378 ALT2 0x1
#define VF610_PAD_PTC5__DSPI1_CS0 0x0C8 0x300 ALT3 0x0
#define VF610_PAD_PTC5__ESAI_SDO3 0x0C8 0x320 ALT4 0x0
#define VF610_PAD_PTC5__ESDHC0_DAT3 0x0C8 0x000 ALT5 0x0
#define VF610_PAD_PTC5__VIU_DATA5 0x0C8 0x000 ALT6 0x0
#define VF610_PAD_PTC5__DCU0_G0 0x0C8 0x000 ALT7 0x0
#define VF610_PAD_PTC6__GPIO_51 0x0CC 0x000 ALT0 0x0
#define VF610_PAD_PTC6__ENET_RMII0_TXD1 0x0CC 0x000 ALT1 0x0
#define VF610_PAD_PTC6__DSPI1_SIN 0x0CC 0x2FC ALT3 0x0
#define VF610_PAD_PTC6__ESAI_SDI0 0x0CC 0x328 ALT4 0x0
#define VF610_PAD_PTC6__ESDHC0_WP 0x0CC 0x000 ALT5 0x0
#define VF610_PAD_PTC6__VIU_DATA6 0x0CC 0x000 ALT6 0x0
#define VF610_PAD_PTC6__DCU0_G1 0x0CC 0x000 ALT7 0x0
#define VF610_PAD_PTC7__GPIO_52 0x0D0 0x000 ALT0 0x0
#define VF610_PAD_PTC7__ENET_RMII0_TXD0 0x0D0 0x000 ALT1 0x0
#define VF610_PAD_PTC7__DSPI1_SOUT 0x0D0 0x000 ALT3 0x0
#define VF610_PAD_PTC7__ESAI_SDI1 0x0D0 0x324 ALT4 0x0
#define VF610_PAD_PTC7__VIU_DATA7 0x0D0 0x000 ALT6 0x0
#define VF610_PAD_PTC7__DCU0_B0 0x0D0 0x000 ALT7 0x0
#define VF610_PAD_PTC8__GPIO_53 0x0D4 0x000 ALT0 0x0
#define VF610_PAD_PTC8__ENET_RMII0_TXEN 0x0D4 0x000 ALT1 0x0
#define VF610_PAD_PTC8__DSPI1_SCK 0x0D4 0x2F8 ALT3 0x0
#define VF610_PAD_PTC8__VIU_DATA8 0x0D4 0x000 ALT6 0x0
#define VF610_PAD_PTC8__DCU0_B1 0x0D4 0x000 ALT7 0x0
#define VF610_PAD_PTC9__GPIO_54 0x0D8 0x000 ALT0 0x0
#define VF610_PAD_PTC9__ENET_RMII1_MDC 0x0D8 0x000 ALT1 0x0
#define VF610_PAD_PTC9__ESAI_SCKT 0x0D8 0x310 ALT3 0x1
#define VF610_PAD_PTC9__MLB_CLK 0x0D8 0x354 ALT6 0x1
#define VF610_PAD_PTC9__DEBUG_OUT0 0x0D8 0x000 ALT7 0x0
#define VF610_PAD_PTC10__GPIO_55 0x0DC 0x000 ALT0 0x0
#define VF610_PAD_PTC10__ENET_RMII1_MDIO 0x0DC 0x000 ALT1 0x0
#define VF610_PAD_PTC10__ESAI_FST 0x0DC 0x30C ALT3 0x1
#define VF610_PAD_PTC10__MLB_SIGNAL 0x0DC 0x35C ALT6 0x1
#define VF610_PAD_PTC10__DEBUG_OUT1 0x0DC 0x000 ALT7 0x0
#define VF610_PAD_PTC11__GPIO_56 0x0E0 0x000 ALT0 0x0
#define VF610_PAD_PTC11__ENET_RMII1_CRS 0x0E0 0x000 ALT1 0x0
#define VF610_PAD_PTC11__ESAI_SDO0 0x0E0 0x314 ALT3 0x1
#define VF610_PAD_PTC11__MLB_DATA 0x0E0 0x358 ALT6 0x1
#define VF610_PAD_PTC11__DEBUG_OUT 0x0E0 0x000 ALT7 0x0
#define VF610_PAD_PTC12__GPIO_57 0x0E4 0x000 ALT0 0x0
#define VF610_PAD_PTC12__ENET_RMII_RXD1 0x0E4 0x000 ALT1 0x0
#define VF610_PAD_PTC12__ESAI_SDO1 0x0E4 0x318 ALT3 0x1
#define VF610_PAD_PTC12__SAI2_TX_BCLK 0x0E4 0x370 ALT5 0x1
#define VF610_PAD_PTC12__DEBUG_OUT3 0x0E4 0x000 ALT7 0x0
#define VF610_PAD_PTC13__GPIO_58 0x0E8 0x000 ALT0 0x0
#define VF610_PAD_PTC13__ENET_RMII1_RXD0 0x0E8 0x000 ALT1 0x0
#define VF610_PAD_PTC13__ESAI_SDO2 0x0E8 0x31C ALT3 0x1
#define VF610_PAD_PTC13__SAI2_RX_BCLK 0x0E8 0x364 ALT5 0x2
#define VF610_PAD_PTC13__DEBUG_OUT4 0x0E8 0x000 ALT7 0x0
#define VF610_PAD_PTC14__GPIO_59 0x0EC 0x000 ALT0 0x0
#define VF610_PAD_PTC14__ENET_RMII1_RXER 0x0EC 0x000 ALT1 0x0
#define VF610_PAD_PTC14__ESAI_SDO3 0x0EC 0x320 ALT3 0x1
#define VF610_PAD_PTC14__UART5_TX 0x0EC 0x000 ALT4 0x0
#define VF610_PAD_PTC14__SAI2_RX_DATA 0x0EC 0x368 ALT5 0x2
#define VF610_PAD_PTC14__ADC0_SE6 0x0EC 0x000 ALT6 0x0
#define VF610_PAD_PTC14__DEBUG_OUT5 0x0EC 0x000 ALT7 0x0
#define VF610_PAD_PTC15__GPIO_60 0x0F0 0x000 ALT0 0x0
#define VF610_PAD_PTC15__ENET_RMII1_TXD1 0x0F0 0x000 ALT1 0x0
#define VF610_PAD_PTC15__ESAI_SDI0 0x0F0 0x328 ALT3 0x1
#define VF610_PAD_PTC15__UART5_RX 0x0F0 0x000 ALT4 0x0
#define VF610_PAD_PTC15__SAI2_TX_DATA 0x0F0 0x000 ALT5 0x0
#define VF610_PAD_PTC15__ADC0_SE7 0x0F0 0x000 ALT6 0x0
#define VF610_PAD_PTC15__DEBUG_OUT6 0x0F0 0x000 ALT7 0x0
#define VF610_PAD_PTC16__GPIO_61 0x0F4 0x000 ALT0 0x0
#define VF610_PAD_PTC16__ENET_RMII1_TXD0 0x0F4 0x000 ALT1 0x0
#define VF610_PAD_PTC16__ESAI_SDI1 0x0F4 0x324 ALT3 0x1
#define VF610_PAD_PTC16__UART5_RTS 0x0F4 0x000 ALT4 0x0
#define VF610_PAD_PTC16__SAI2_RX_SYNC 0x0F4 0x36C ALT5 0x2
#define VF610_PAD_PTC16__ADC1_SE6 0x0F4 0x000 ALT6 0x0
#define VF610_PAD_PTC16__DEBUG_OUT7 0x0F4 0x000 ALT7 0x0
#define VF610_PAD_PTC17__GPIO_62 0x0F8 0x000 ALT0 0x0
#define VF610_PAD_PTC17__ENET_RMII1_TXEN 0x0F8 0x000 ALT1 0x0
#define VF610_PAD_PTC17__ADC1_SE7 0x0F8 0x000 ALT3 0x0
#define VF610_PAD_PTC17__UART5_CTS 0x0F8 0x000 ALT4 0x0
#define VF610_PAD_PTC17__SAI2_TX_SYNC 0x0F8 0x374 ALT5 0x1
#define VF610_PAD_PTC17__USB1_SOF_PULSE 0x0F8 0x000 ALT6 0x0
#define VF610_PAD_PTC17__DEBUG_OUT8 0x0F8 0x000 ALT7 0x0
#define VF610_PAD_PTD31__GPIO_63 0x0FC 0x000 ALT0 0x0
#define VF610_PAD_PTD31__FB_AD31 0x0FC 0x000 ALT1 0x0
#define VF610_PAD_PTD31__NF_IO15 0x0FC 0x000 ALT2 0x0
#define VF610_PAD_PTD31__FTM3_CH0 0x0FC 0x000 ALT4 0x0
#define VF610_PAD_PTD31__DSPI2_CS1 0x0FC 0x000 ALT5 0x0
#define VF610_PAD_PTD31__DEBUG_OUT9 0x0FC 0x000 ALT7 0x0
#define VF610_PAD_PTD30__GPIO_64 0x100 0x000 ALT0 0x0
#define VF610_PAD_PTD30__FB_AD30 0x100 0x000 ALT1 0x0
#define VF610_PAD_PTD30__NF_IO14 0x100 0x000 ALT2 0x0
#define VF610_PAD_PTD30__FTM3_CH1 0x100 0x000 ALT4 0x0
#define VF610_PAD_PTD30__DSPI2_CS0 0x100 0x000 ALT5 0x0
#define VF610_PAD_PTD30__DEBUG_OUT10 0x100 0x000 ALT7 0x0
#define VF610_PAD_PTD29__GPIO_65 0x104 0x000 ALT0 0x0
#define VF610_PAD_PTD29__FB_AD29 0x104 0x000 ALT1 0x0
#define VF610_PAD_PTD29__NF_IO13 0x104 0x000 ALT2 0x0
#define VF610_PAD_PTD29__FTM3_CH2 0x104 0x000 ALT4 0x0
#define VF610_PAD_PTD29__DSPI2_SIN 0x104 0x000 ALT5 0x0
#define VF610_PAD_PTD29__DEBUG_OUT11 0x104 0x000 ALT7 0x0
#define VF610_PAD_PTD28__GPIO_66 0x108 0x000 ALT0 0x0
#define VF610_PAD_PTD28__FB_AD28 0x108 0x000 ALT1 0x0
#define VF610_PAD_PTD28__NF_IO12 0x108 0x000 ALT2 0x0
#define VF610_PAD_PTD28__I2C2_SCL 0x108 0x34C ALT3 0x1
#define VF610_PAD_PTD28__FTM3_CH3 0x108 0x000 ALT4 0x0
#define VF610_PAD_PTD28__DSPI2_SOUT 0x108 0x000 ALT5 0x0
#define VF610_PAD_PTD28__DEBUG_OUT12 0x108 0x000 ALT7 0x0
#define VF610_PAD_PTD27__GPIO_67 0x10C 0x000 ALT0 0x0
#define VF610_PAD_PTD27__FB_AD27 0x10C 0x000 ALT1 0x0
#define VF610_PAD_PTD27__NF_IO11 0x10C 0x000 ALT2 0x0
#define VF610_PAD_PTD27__I2C2_SDA 0x10C 0x350 ALT3 0x1
#define VF610_PAD_PTD27__FTM3_CH4 0x10C 0x000 ALT4 0x0
#define VF610_PAD_PTD27__DSPI2_SCK 0x10C 0x000 ALT5 0x0
#define VF610_PAD_PTD27__DEBUG_OUT13 0x10C 0x000 ALT7 0x0
#define VF610_PAD_PTD26__GPIO_68 0x110 0x000 ALT0 0x0
#define VF610_PAD_PTD26__FB_AD26 0x110 0x000 ALT1 0x0
#define VF610_PAD_PTD26__NF_IO10 0x110 0x000 ALT2 0x0
#define VF610_PAD_PTD26__FTM3_CH5 0x110 0x000 ALT4 0x0
#define VF610_PAD_PTD26__ESDHC1_WP 0x110 0x000 ALT5 0x0
#define VF610_PAD_PTD26__DEBUG_OUT14 0x110 0x000 ALT7 0x0
#define VF610_PAD_PTD25__GPIO_69 0x114 0x000 ALT0 0x0
#define VF610_PAD_PTD25__FB_AD25 0x114 0x000 ALT1 0x0
#define VF610_PAD_PTD25__NF_IO9 0x114 0x000 ALT2 0x0
#define VF610_PAD_PTD25__FTM3_CH6 0x114 0x000 ALT4 0x0
#define VF610_PAD_PTD25__DEBUG_OUT15 0x114 0x000 ALT7 0x0
#define VF610_PAD_PTD24__GPIO_70 0x118 0x000 ALT0 0x0
#define VF610_PAD_PTD24__FB_AD24 0x118 0x000 ALT1 0x0
#define VF610_PAD_PTD24__NF_IO8 0x118 0x000 ALT2 0x0
#define VF610_PAD_PTD24__FTM3_CH7 0x118 0x000 ALT4 0x0
#define VF610_PAD_PTD24__DEBUG_OUT16 0x118 0x000 ALT7 0x0
#define VF610_PAD_PTD23__GPIO_71 0x11C 0x000 ALT0 0x0
#define VF610_PAD_PTD23__FB_AD23 0x11C 0x000 ALT1 0x0
#define VF610_PAD_PTD23__NF_IO7 0x11C 0x000 ALT2 0x0
#define VF610_PAD_PTD23__FTM2_CH0 0x11C 0x000 ALT3 0x0
#define VF610_PAD_PTD23__ENET0_1588_TMR0 0x11C 0x304 ALT4 0x1
#define VF610_PAD_PTD23__ESDHC0_DAT4 0x11C 0x000 ALT5 0x0
#define VF610_PAD_PTD23__UART2_TX 0x11C 0x38C ALT6 0x1
#define VF610_PAD_PTD23__DCU1_R3 0x11C 0x000 ALT7 0x0
#define VF610_PAD_PTD22__GPIO_72 0x120 0x000 ALT0 0x0
#define VF610_PAD_PTD22__FB_AD22 0x120 0x000 ALT1 0x0
#define VF610_PAD_PTD22__NF_IO6 0x120 0x000 ALT2 0x0
#define VF610_PAD_PTD22__FTM2_CH1 0x120 0x000 ALT3 0x0
#define VF610_PAD_PTD22__ENET0_1588_TMR1 0x120 0x308 ALT4 0x1
#define VF610_PAD_PTD22__ESDHC0_DAT5 0x120 0x000 ALT5 0x0
#define VF610_PAD_PTD22__UART2_RX 0x120 0x388 ALT6 0x1
#define VF610_PAD_PTD22__DCU1_R4 0x120 0x000 ALT7 0x0
#define VF610_PAD_PTD21__GPIO_73 0x124 0x000 ALT0 0x0
#define VF610_PAD_PTD21__FB_AD21 0x124 0x000 ALT1 0x0
#define VF610_PAD_PTD21__NF_IO5 0x124 0x000 ALT2 0x0
#define VF610_PAD_PTD21__ENET0_1588_TMR2 0x124 0x000 ALT4 0x0
#define VF610_PAD_PTD21__ESDHC0_DAT6 0x124 0x000 ALT5 0x0
#define VF610_PAD_PTD21__UART2_RTS 0x124 0x000 ALT6 0x0
#define VF610_PAD_PTD21__DCU1_R5 0x124 0x000 ALT7 0x0
#define VF610_PAD_PTD20__GPIO_74 0x128 0x000 ALT0 0x0
#define VF610_PAD_PTD20__FB_AD20 0x128 0x000 ALT1 0x0
#define VF610_PAD_PTD20__NF_IO4 0x128 0x000 ALT2 0x0
#define VF610_PAD_PTD20__ENET0_1588_TMR3 0x128 0x000 ALT4 0x0
#define VF610_PAD_PTD20__ESDHC0_DAT7 0x128 0x000 ALT5 0x0
#define VF610_PAD_PTD20__UART2_CTS 0x128 0x384 ALT6 0x0
#define VF610_PAD_PTD20__DCU1_R0 0x128 0x000 ALT7 0x0
#define VF610_PAD_PTD19__GPIO_75 0x12C 0x000 ALT0 0x0
#define VF610_PAD_PTD19__FB_AD19 0x12C 0x000 ALT1 0x0
#define VF610_PAD_PTD19__NF_IO3 0x12C 0x000 ALT2 0x0
#define VF610_PAD_PTD19__ESAI_SCKR 0x12C 0x000 ALT3 0x0
#define VF610_PAD_PTD19__I2C0_SCL 0x12C 0x33C ALT4 0x2
#define VF610_PAD_PTD19__FTM2_QD_PHA 0x12C 0x000 ALT5 0x0
#define VF610_PAD_PTD19__DCU1_R1 0x12C 0x000 ALT7 0x0
#define VF610_PAD_PTD18__GPIO_76 0x130 0x000 ALT0 0x0
#define VF610_PAD_PTD18__FB_AD18 0x130 0x000 ALT1 0x0
#define VF610_PAD_PTD18__NF_IO2 0x130 0x000 ALT2 0x0
#define VF610_PAD_PTD18__ESAI_FSR 0x130 0x000 ALT3 0x0
#define VF610_PAD_PTD18__I2C0_SDA 0x130 0x340 ALT4 0x2
#define VF610_PAD_PTD18__FTM2_QD_PHB 0x130 0x000 ALT5 0x0
#define VF610_PAD_PTD18__DCU1_G0 0x130 0x000 ALT7 0x0
#define VF610_PAD_PTD17__GPIO_77 0x134 0x000 ALT0 0x0
#define VF610_PAD_PTD17__FB_AD17 0x134 0x000 ALT1 0x0
#define VF610_PAD_PTD17__NF_IO1 0x134 0x000 ALT2 0x0
#define VF610_PAD_PTD17__ESAI_HCKR 0x134 0x000 ALT3 0x0
#define VF610_PAD_PTD17__I2C1_SCL 0x134 0x344 ALT4 0x2
#define VF610_PAD_PTD17__DCU1_G1 0x134 0x000 ALT7 0x0
#define VF610_PAD_PTD16__GPIO_78 0x138 0x000 ALT0 0x0
#define VF610_PAD_PTD16__FB_AD16 0x138 0x000 ALT1 0x0
#define VF610_PAD_PTD16__NF_IO0 0x138 0x000 ALT2 0x0
#define VF610_PAD_PTD16__ESAI_HCKT 0x138 0x000 ALT3 0x0
#define VF610_PAD_PTD16__I2C1_SDA 0x138 0x348 ALT4 0x2
#define VF610_PAD_PTD16__DCU1_G2 0x138 0x000 ALT7 0x0
#define VF610_PAD_PTD0__GPIO_79 0x13C 0x000 ALT0 0x0
#define VF610_PAD_PTD0__QSPI0_A_QSCK 0x13C 0x000 ALT1 0x0
#define VF610_PAD_PTD0__UART2_TX 0x13C 0x38C ALT2 0x2
#define VF610_PAD_PTD0__FB_AD15 0x13C 0x000 ALT4 0x0
#define VF610_PAD_PTD0__SPDIF_EXTCLK 0x13C 0x000 ALT5 0x0
#define VF610_PAD_PTD0__DEBUG_OUT17 0x13C 0x000 ALT7 0x0
#define VF610_PAD_PTD1__GPIO_80 0x140 0x000 ALT0 0x0
#define VF610_PAD_PTD1__QSPI0_A_CS0 0x140 0x000 ALT1 0x0
#define VF610_PAD_PTD1__UART2_RX 0x140 0x388 ALT2 0x2
#define VF610_PAD_PTD1__FB_AD14 0x140 0x000 ALT4 0x0
#define VF610_PAD_PTD1__SPDIF_IN1 0x140 0x000 ALT5 0x0
#define VF610_PAD_PTD1__DEBUG_OUT18 0x140 0x000 ALT7 0x0
#define VF610_PAD_PTD2__GPIO_81 0x144 0x000 ALT0 0x0
#define VF610_PAD_PTD2__QSPI0_A_DATA3 0x144 0x000 ALT1 0x0
#define VF610_PAD_PTD2__UART2_RTS 0x144 0x000 ALT2 0x0
#define VF610_PAD_PTD2__DSPI1_CS3 0x144 0x000 ALT3 0x0
#define VF610_PAD_PTD2__FB_AD13 0x144 0x000 ALT4 0x0
#define VF610_PAD_PTD2__SPDIF_OUT1 0x144 0x000 ALT5 0x0
#define VF610_PAD_PTD2__DEBUG_OUT19 0x144 0x000 ALT7 0x0
#define VF610_PAD_PTD3__GPIO_82 0x148 0x000 ALT0 0x0
#define VF610_PAD_PTD3__QSPI0_A_DATA2 0x148 0x000 ALT1 0x0
#define VF610_PAD_PTD3__UART2_CTS 0x148 0x384 ALT2 0x1
#define VF610_PAD_PTD3__DSPI1_CS2 0x148 0x000 ALT3 0x0
#define VF610_PAD_PTD3__FB_AD12 0x148 0x000 ALT4 0x0
#define VF610_PAD_PTD3__SPDIF_PLOCK 0x148 0x000 ALT5 0x0
#define VF610_PAD_PTD3__DEBUG_OUT20 0x148 0x000 ALT7 0x0
#define VF610_PAD_PTD4__GPIO_83 0x14C 0x000 ALT0 0x0
#define VF610_PAD_PTD4__QSPI0_A_DATA1 0x14C 0x000 ALT1 0x0
#define VF610_PAD_PTD4__DSPI1_CS1 0x14C 0x000 ALT3 0x0
#define VF610_PAD_PTD4__FB_AD11 0x14C 0x000 ALT4 0x0
#define VF610_PAD_PTD4__SPDIF_SRCLK 0x14C 0x000 ALT5 0x0
#define VF610_PAD_PTD4__DEBUG_OUT21 0x14C 0x000 ALT7 0x0
#define VF610_PAD_PTD5__GPIO_84 0x150 0x000 ALT0 0x0
#define VF610_PAD_PTD5__QSPI0_A_DATA0 0x150 0x000 ALT1 0x0
#define VF610_PAD_PTD5__DSPI1_CS0 0x150 0x300 ALT3 0x1
#define VF610_PAD_PTD5__FB_AD10 0x150 0x000 ALT4 0x0
#define VF610_PAD_PTD5__DEBUG_OUT22 0x150 0x000 ALT7 0x0
#define VF610_PAD_PTD6__GPIO_85 0x154 0x000 ALT0 0x0
#define VF610_PAD_PTD6__QSPI1_A_DQS 0x154 0x000 ALT1 0x0
#define VF610_PAD_PTD6__DSPI1_SIN 0x154 0x2FC ALT3 0x1
#define VF610_PAD_PTD6__FB_AD9 0x154 0x000 ALT4 0x0
#define VF610_PAD_PTD6__DEBUG_OUT23 0x154 0x000 ALT7 0x0
#define VF610_PAD_PTD7__GPIO_86 0x158 0x000 ALT0 0x0
#define VF610_PAD_PTD7__QSPI0_B_QSCK 0x158 0x000 ALT1 0x0
#define VF610_PAD_PTD7__DSPI1_SOUT 0x158 0x000 ALT3 0x0
#define VF610_PAD_PTD7__FB_AD8 0x158 0x000 ALT4 0x0
#define VF610_PAD_PTD7__DEBUG_OUT24 0x158 0x000 ALT7 0x0
#define VF610_PAD_PTD8__GPIO_87 0x15C 0x000 ALT0 0x0
#define VF610_PAD_PTD8__QSPI0_B_CS0 0x15C 0x000 ALT1 0x0
#define VF610_PAD_PTD8__FB_CLKOUT 0x15C 0x000 ALT2 0x0
#define VF610_PAD_PTD8__DSPI1_SCK 0x15C 0x2F8 ALT3 0x1
#define VF610_PAD_PTD8__FB_AD7 0x15C 0x000 ALT4 0x0
#define VF610_PAD_PTD8__DEBUG_OUT25 0x15C 0x000 ALT7 0x0
#define VF610_PAD_PTD9__GPIO_88 0x160 0x000 ALT0 0x0
#define VF610_PAD_PTD9__QSPI0_B_DATA3 0x160 0x000 ALT1 0x0
#define VF610_PAD_PTD9__DSPI3_CS1 0x160 0x000 ALT2 0x0
#define VF610_PAD_PTD9__FB_AD6 0x160 0x000 ALT4 0x0
#define VF610_PAD_PTD9__SAI1_TX_SYNC 0x160 0x360 ALT6 0x0
#define VF610_PAD_PTD9__DCU1_B0 0x160 0x000 ALT7 0x0
#define VF610_PAD_PTD10__GPIO_89 0x164 0x000 ALT0 0x0
#define VF610_PAD_PTD10__QSPI0_B_DATA2 0x164 0x000 ALT1 0x0
#define VF610_PAD_PTD10__DSPI3_CS0 0x164 0x000 ALT2 0x0
#define VF610_PAD_PTD10__FB_AD5 0x164 0x000 ALT4 0x0
#define VF610_PAD_PTD10__DCU1_B1 0x164 0x000 ALT7 0x0
#define VF610_PAD_PTD11__GPIO_90 0x168 0x000 ALT0 0x0
#define VF610_PAD_PTD11__QSPI0_B_DATA1 0x168 0x000 ALT1 0x0
#define VF610_PAD_PTD11__DSPI3_SIN 0x168 0x000 ALT2 0x0
#define VF610_PAD_PTD11__FB_AD4 0x168 0x000 ALT4 0x0
#define VF610_PAD_PTD11__DEBUG_OUT26 0x168 0x000 ALT7 0x0
#define VF610_PAD_PTD12__GPIO_91 0x16C 0x000 ALT0 0x0
#define VF610_PAD_PTD12__QSPI0_B_DATA0 0x16C 0x000 ALT1 0x0
#define VF610_PAD_PTD12__DSPI3_SOUT 0x16C 0x000 ALT2 0x0
#define VF610_PAD_PTD12__FB_AD3 0x16C 0x000 ALT4 0x0
#define VF610_PAD_PTD12__DEBUG_OUT27 0x16C 0x000 ALT7 0x0
#define VF610_PAD_PTD13__GPIO_92 0x170 0x000 ALT0 0x0
#define VF610_PAD_PTD13__QSPI0_B_DQS 0x170 0x000 ALT1 0x0
#define VF610_PAD_PTD13__DSPI3_SCK 0x170 0x000 ALT2 0x0
#define VF610_PAD_PTD13__FB_AD2 0x170 0x000 ALT4 0x0
#define VF610_PAD_PTD13__DEBUG_OUT28 0x170 0x000 ALT7 0x0
#define VF610_PAD_PTB23__GPIO_93 0x174 0x000 ALT0 0x0
#define VF610_PAD_PTB23__SAI0_TX_BCLK 0x174 0x000 ALT1 0x0
#define VF610_PAD_PTB23__UART1_TX 0x174 0x380 ALT2 0x2
#define VF610_PAD_PTB23__SRC_RCON18 0x174 0x398 ALT3 0x1
#define VF610_PAD_PTB23__FB_MUXED_ALE 0x174 0x000 ALT4 0x0
#define VF610_PAD_PTB23__FB_TS_B 0x174 0x000 ALT5 0x0
#define VF610_PAD_PTB23__UART3_RTS 0x174 0x000 ALT6 0x0
#define VF610_PAD_PTB23__DCU1_G3 0x174 0x000 ALT7 0x0
#define VF610_PAD_PTB24__GPIO_94 0x178 0x000 ALT0 0x0
#define VF610_PAD_PTB24__SAI0_RX_BCLK 0x178 0x000 ALT1 0x0
#define VF610_PAD_PTB24__UART1_RX 0x178 0x37C ALT2 0x2
#define VF610_PAD_PTB24__SRC_RCON19 0x178 0x39C ALT3 0x1
#define VF610_PAD_PTB24__FB_MUXED_TSIZ0 0x178 0x000 ALT4 0x0
#define VF610_PAD_PTB24__NF_WE_B 0x178 0x000 ALT5 0x0
#define VF610_PAD_PTB24__UART3_CTS 0x178 0x000 ALT6 0x0
#define VF610_PAD_PTB24__DCU1_G4 0x178 0x000 ALT7 0x0
#define VF610_PAD_PTB25__GPIO_95 0x17C 0x000 ALT0 0x0
#define VF610_PAD_PTB25__SAI0_RX_DATA 0x17C 0x000 ALT1 0x0
#define VF610_PAD_PTB25__UART1_RTS 0x17C 0x000 ALT2 0x0
#define VF610_PAD_PTB25__SRC_RCON20 0x17C 0x3A0 ALT3 0x1
#define VF610_PAD_PTB25__FB_CS1_B 0x17C 0x000 ALT4 0x0
#define VF610_PAD_PTB25__NF_CE0_B 0x17C 0x000 ALT5 0x0
#define VF610_PAD_PTB25__DCU1_G5 0x17C 0x000 ALT7 0x0
#define VF610_PAD_PTB26__GPIO_96 0x180 0x000 ALT0 0x0
#define VF610_PAD_PTB26__SAI0_TX_DATA 0x180 0x000 ALT1 0x0
#define VF610_PAD_PTB26__UART1_CTS 0x180 0x378 ALT2 0x2
#define VF610_PAD_PTB26__SRC_RCON21 0x180 0x000 ALT3 0x0
#define VF610_PAD_PTB26__FB_CS0_B 0x180 0x000 ALT4 0x0
#define VF610_PAD_PTB26__NF_CE1_B 0x180 0x000 ALT5 0x0
#define VF610_PAD_PTB26__DCU1_G6 0x180 0x000 ALT7 0x0
#define VF610_PAD_PTB27__GPIO_97 0x184 0x000 ALT0 0x0
#define VF610_PAD_PTB27__SAI0_RX_SYNC 0x184 0x000 ALT1 0x0
#define VF610_PAD_PTB27__SRC_RCON22 0x184 0x000 ALT3 0x0
#define VF610_PAD_PTB27__FB_OE_B 0x184 0x000 ALT4 0x0
#define VF610_PAD_PTB27__FB_MUXED_TBST_B 0x184 0x000 ALT5 0x0
#define VF610_PAD_PTB27__NF_RE_B 0x184 0x000 ALT6 0x0
#define VF610_PAD_PTB27__DCU1_G7 0x184 0x000 ALT7 0x0
#define VF610_PAD_PTB28__GPIO_98 0x188 0x000 ALT0 0x0
#define VF610_PAD_PTB28__SAI0_TX_SYNC 0x188 0x000 ALT1 0x0
#define VF610_PAD_PTB28__SRC_RCON23 0x188 0x000 ALT3 0x0
#define VF610_PAD_PTB28__FB_RW_B 0x188 0x000 ALT4 0x0
#define VF610_PAD_PTB28__DCU1_B6 0x188 0x000 ALT7 0x0
#define VF610_PAD_PTC26__GPIO_99 0x18C 0x000 ALT0 0x0
#define VF610_PAD_PTC26__SAI1_TX_BCLK 0x18C 0x000 ALT1 0x0
#define VF610_PAD_PTC26__DSPI0_CS5 0x18C 0x000 ALT2 0x0
#define VF610_PAD_PTC26__SRC_RCON24 0x18C 0x000 ALT3 0x0
#define VF610_PAD_PTC26__FB_TA_B 0x18C 0x000 ALT4 0x0
#define VF610_PAD_PTC26__NF_RB_B 0x18C 0x000 ALT5 0x0
#define VF610_PAD_PTC26__DCU1_B7 0x18C 0x000 ALT7 0x0
#define VF610_PAD_PTC27__GPIO_100 0x190 0x000 ALT0 0x0
#define VF610_PAD_PTC27__SAI1_RX_BCLK 0x190 0x000 ALT1 0x0
#define VF610_PAD_PTC27__DSPI0_CS4 0x190 0x000 ALT2 0x0
#define VF610_PAD_PTC27__SRC_RCON25 0x190 0x000 ALT3 0x0
#define VF610_PAD_PTC27__FB_BE3_B 0x190 0x000 ALT4 0x0
#define VF610_PAD_PTC27__FB_CS3_B 0x190 0x000 ALT5 0x0
#define VF610_PAD_PTC27__NF_ALE 0x190 0x000 ALT6 0x0
#define VF610_PAD_PTC27__DCU1_B2 0x190 0x000 ALT7 0x0
#define VF610_PAD_PTC28__GPIO_101 0x194 0x000 ALT0 0x0
#define VF610_PAD_PTC28__SAI1_RX_DATA 0x194 0x000 ALT1 0x0
#define VF610_PAD_PTC28__DSPI0_CS3 0x194 0x000 ALT2 0x0
#define VF610_PAD_PTC28__SRC_RCON26 0x194 0x000 ALT3 0x0
#define VF610_PAD_PTC28__FB_BE2_B 0x194 0x000 ALT4 0x0
#define VF610_PAD_PTC28__FB_CS2_B 0x194 0x000 ALT5 0x0
#define VF610_PAD_PTC28__NF_CLE 0x194 0x000 ALT6 0x0
#define VF610_PAD_PTC28__DCU1_B3 0x194 0x000 ALT7 0x0
#define VF610_PAD_PTC29__GPIO_102 0x198 0x000 ALT0 0x0
#define VF610_PAD_PTC29__SAI1_TX_DATA 0x198 0x000 ALT1 0x0
#define VF610_PAD_PTC29__DSPI0_CS2 0x198 0x000 ALT2 0x0
#define VF610_PAD_PTC29__SRC_RCON27 0x198 0x000 ALT3 0x0
#define VF610_PAD_PTC29__FB_BE1_B 0x198 0x000 ALT4 0x0
#define VF610_PAD_PTC29__FB_MUXED_TSIZE1 0x198 0x000 ALT5 0x0
#define VF610_PAD_PTC29__DCU1_B4 0x198 0x000 ALT7 0x0
#define VF610_PAD_PTC30__GPIO_103 0x19C 0x000 ALT0 0x0
#define VF610_PAD_PTC30__SAI1_RX_SYNC 0x19C 0x000 ALT1 0x0
#define VF610_PAD_PTC30__DSPI1_CS2 0x19C 0x000 ALT2 0x0
#define VF610_PAD_PTC30__SRC_RCON28 0x19C 0x000 ALT3 0x0
#define VF610_PAD_PTC30__FB_MUXED_BE0_B 0x19C 0x000 ALT4 0x0
#define VF610_PAD_PTC30__FB_TSIZ0 0x19C 0x000 ALT5 0x0
#define VF610_PAD_PTC30__ADC0_SE5 0x19C 0x000 ALT6 0x0
#define VF610_PAD_PTC30__DCU1_B5 0x19C 0x000 ALT7 0x0
#define VF610_PAD_PTC31__GPIO_104 0x1A0 0x000 ALT0 0x0
#define VF610_PAD_PTC31__SAI1_TX_SYNC 0x1A0 0x360 ALT1 0x1
#define VF610_PAD_PTC31__SRC_RCON29 0x1A0 0x000 ALT3 0x0
#define VF610_PAD_PTC31__ADC1_SE5 0x1A0 0x000 ALT6 0x0
#define VF610_PAD_PTC31__DCU1_B6 0x1A0 0x000 ALT7 0x0
#define VF610_PAD_PTE0__GPIO_105 0x1A4 0x000 ALT0 0x0
#define VF610_PAD_PTE0__DCU0_HSYNC 0x1A4 0x000 ALT1 0x0
#define VF610_PAD_PTE0__SRC_BMODE1 0x1A4 0x000 ALT2 0x0
#define VF610_PAD_PTE0__LCD0 0x1A4 0x000 ALT4 0x0
#define VF610_PAD_PTE0__DEBUG_OUT29 0x1A4 0x000 ALT7 0x0
#define VF610_PAD_PTE1__GPIO_106 0x1A8 0x000 ALT0 0x0
#define VF610_PAD_PTE1__DCU0_VSYNC 0x1A8 0x000 ALT1 0x0
#define VF610_PAD_PTE1__SRC_BMODE0 0x1A8 0x000 ALT2 0x0
#define VF610_PAD_PTE1__LCD1 0x1A8 0x000 ALT4 0x0
#define VF610_PAD_PTE1__DEBUG_OUT30 0x1A8 0x000 ALT7 0x0
#define VF610_PAD_PTE2__GPIO_107 0x1AC 0x000 ALT0 0x0
#define VF610_PAD_PTE2__DCU0_PCLK 0x1AC 0x000 ALT1 0x0
#define VF610_PAD_PTE2__LCD2 0x1AC 0x000 ALT4 0x0
#define VF610_PAD_PTE2__DEBUG_OUT31 0x1AC 0x000 ALT7 0x0
#define VF610_PAD_PTE3__GPIO_108 0x1B0 0x000 ALT0 0x0
#define VF610_PAD_PTE3__DCU0_TAG 0x1B0 0x000 ALT1 0x0
#define VF610_PAD_PTE3__LCD3 0x1B0 0x000 ALT4 0x0
#define VF610_PAD_PTE3__DEBUG_OUT32 0x1B0 0x000 ALT7 0x0
#define VF610_PAD_PTE4__GPIO_109 0x1B4 0x000 ALT0 0x0
#define VF610_PAD_PTE4__DCU0_DE 0x1B4 0x000 ALT1 0x0
#define VF610_PAD_PTE4__LCD4 0x1B4 0x000 ALT4 0x0
#define VF610_PAD_PTE4__DEBUG_OUT33 0x1B4 0x000 ALT7 0x0
#define VF610_PAD_PTE5__GPIO_110 0x1B8 0x000 ALT0 0x0
#define VF610_PAD_PTE5__DCU0_R0 0x1B8 0x000 ALT1 0x0
#define VF610_PAD_PTE5__LCD5 0x1B8 0x000 ALT4 0x0
#define VF610_PAD_PTE5__DEBUG_OUT34 0x1B8 0x000 ALT7 0x0
#define VF610_PAD_PTE6__GPIO_111 0x1BC 0x000 ALT0 0x0
#define VF610_PAD_PTE6__DCU0_R1 0x1BC 0x000 ALT1 0x0
#define VF610_PAD_PTE6__LCD6 0x1BC 0x000 ALT4 0x0
#define VF610_PAD_PTE6__DEBUG_OUT35 0x1BC 0x000 ALT7 0x0
#define VF610_PAD_PTE7__GPIO_112 0x1C0 0x000 ALT0 0x0
#define VF610_PAD_PTE7__DCU0_R2 0x1C0 0x000 ALT1 0x0
#define VF610_PAD_PTE7__SRC_RCON0 0x1C0 0x000 ALT3 0x0
#define VF610_PAD_PTE7__LCD7 0x1C0 0x000 ALT4 0x0
#define VF610_PAD_PTE7__DEBUG_OUT36 0x1C0 0x000 ALT7 0x0
#define VF610_PAD_PTE8__GPIO_113 0x1C4 0x000 ALT0 0x0
#define VF610_PAD_PTE8__DCU0_R3 0x1C4 0x000 ALT1 0x0
#define VF610_PAD_PTE8__SRC_RCON1 0x1C4 0x000 ALT3 0x0
#define VF610_PAD_PTE8__LCD8 0x1C4 0x000 ALT4 0x0
#define VF610_PAD_PTE8__DEBUG_OUT37 0x1C4 0x000 ALT7 0x0
#define VF610_PAD_PTE9__GPIO_114 0x1C8 0x000 ALT0 0x0
#define VF610_PAD_PTE9__DCU0_R4 0x1C8 0x000 ALT1 0x0
#define VF610_PAD_PTE9__SRC_RCON2 0x1C8 0x000 ALT3 0x0
#define VF610_PAD_PTE9__LCD9 0x1C8 0x000 ALT4 0x0
#define VF610_PAD_PTE9__DEBUG_OUT38 0x1C8 0x000 ALT7 0x0
#define VF610_PAD_PTE10__GPIO_115 0x1CC 0x000 ALT0 0x0
#define VF610_PAD_PTE10__DCU0_R5 0x1CC 0x000 ALT1 0x0
#define VF610_PAD_PTE10__SRC_RCON3 0x1CC 0x000 ALT3 0x0
#define VF610_PAD_PTE10__LCD10 0x1CC 0x000 ALT4 0x0
#define VF610_PAD_PTE10__DEBUG_OUT39 0x1CC 0x000 ALT7 0x0
#define VF610_PAD_PTE11__GPIO_116 0x1D0 0x000 ALT0 0x0
#define VF610_PAD_PTE11__DCU0_R6 0x1D0 0x000 ALT1 0x0
#define VF610_PAD_PTE11__SRC_RCON4 0x1D0 0x000 ALT3 0x0
#define VF610_PAD_PTE11__LCD11 0x1D0 0x000 ALT4 0x0
#define VF610_PAD_PTE11__DEBUG_OUT40 0x1D0 0x000 ALT7 0x0
#define VF610_PAD_PTE12__GPIO_117 0x1D4 0x000 ALT0 0x0
#define VF610_PAD_PTE12__DCU0_R7 0x1D4 0x000 ALT1 0x0
#define VF610_PAD_PTE12__DSPI1_CS3 0x1D4 0x000 ALT2 0x0
#define VF610_PAD_PTE12__SRC_RCON5 0x1D4 0x000 ALT3 0x0
#define VF610_PAD_PTE12__LCD12 0x1D4 0x000 ALT4 0x0
#define VF610_PAD_PTE12__LPT_ALT0 0x1D4 0x000 ALT7 0x0
#define VF610_PAD_PTE13__GPIO_118 0x1D8 0x000 ALT0 0x0
#define VF610_PAD_PTE13__DCU0_G0 0x1D8 0x000 ALT1 0x0
#define VF610_PAD_PTE13__LCD13 0x1D8 0x000 ALT4 0x0
#define VF610_PAD_PTE13__DEBUG_OUT41 0x1D8 0x000 ALT7 0x0
#define VF610_PAD_PTE14__GPIO_119 0x1DC 0x000 ALT0 0x0
#define VF610_PAD_PTE14__DCU0_G1 0x1DC 0x000 ALT1 0x0
#define VF610_PAD_PTE14__LCD14 0x1DC 0x000 ALT4 0x0
#define VF610_PAD_PTE14__DEBUG_OUT42 0x1DC 0x000 ALT7 0x0
#define VF610_PAD_PTE15__GPIO_120 0x1E0 0x000 ALT0 0x0
#define VF610_PAD_PTE15__DCU0_G2 0x1E0 0x000 ALT1 0x0
#define VF610_PAD_PTE15__SRC_RCON6 0x1E0 0x000 ALT3 0x0
#define VF610_PAD_PTE15__LCD15 0x1E0 0x000 ALT4 0x0
#define VF610_PAD_PTE15__DEBUG_OUT43 0x1E0 0x000 ALT7 0x0
#define VF610_PAD_PTE16__GPIO_121 0x1E4 0x000 ALT0 0x0
#define VF610_PAD_PTE16__DCU0_G3 0x1E4 0x000 ALT1 0x0
#define VF610_PAD_PTE16__SRC_RCON7 0x1E4 0x000 ALT3 0x0
#define VF610_PAD_PTE16__LCD16 0x1E4 0x000 ALT4 0x0
#define VF610_PAD_PTE17__GPIO_122 0x1E8 0x000 ALT0 0x0
#define VF610_PAD_PTE17__DCU0_G4 0x1E8 0x000 ALT1 0x0
#define VF610_PAD_PTE17__SRC_RCON8 0x1E8 0x000 ALT3 0x0
#define VF610_PAD_PTE17__LCD17 0x1E8 0x000 ALT4 0x0
#define VF610_PAD_PTE18__GPIO_123 0x1EC 0x000 ALT0 0x0
#define VF610_PAD_PTE18__DCU0_G5 0x1EC 0x000 ALT1 0x0
#define VF610_PAD_PTE18__SRC_RCON9 0x1EC 0x000 ALT3 0x0
#define VF610_PAD_PTE18__LCD18 0x1EC 0x000 ALT4 0x0
#define VF610_PAD_PTE19__GPIO_124 0x1F0 0x000 ALT0 0x0
#define VF610_PAD_PTE19__DCU0_G6 0x1F0 0x000 ALT1 0x0
#define VF610_PAD_PTE19__SRC_RCON10 0x1F0 0x000 ALT3 0x0
#define VF610_PAD_PTE19__LCD19 0x1F0 0x000 ALT4 0x0
#define VF610_PAD_PTE19__I2C0_SCL 0x1F0 0x33C ALT5 0x3
#define VF610_PAD_PTE20__GPIO_125 0x1F4 0x000 ALT0 0x0
#define VF610_PAD_PTE20__DCU0_G7 0x1F4 0x000 ALT1 0x0
#define VF610_PAD_PTE20__SRC_RCON11 0x1F4 0x000 ALT3 0x0
#define VF610_PAD_PTE20__LCD20 0x1F4 0x000 ALT4 0x0
#define VF610_PAD_PTE20__I2C0_SDA 0x1F4 0x340 ALT5 0x3
#define VF610_PAD_PTE20__EWM_IN 0x1F4 0x000 ALT7 0x0
#define VF610_PAD_PTE21__GPIO_126 0x1F8 0x000 ALT0 0x0
#define VF610_PAD_PTE21__DCU0_B0 0x1F8 0x000 ALT1 0x0
#define VF610_PAD_PTE21__LCD21 0x1F8 0x000 ALT4 0x0
#define VF610_PAD_PTE22__GPIO_127 0x1FC 0x000 ALT0 0x0
#define VF610_PAD_PTE22__DCU0_B1 0x1FC 0x000 ALT1 0x0
#define VF610_PAD_PTE22__LCD22 0x1FC 0x000 ALT4 0x0
#define VF610_PAD_PTE23__GPIO_128 0x200 0x000 ALT0 0x0
#define VF610_PAD_PTE23__DCU0_B2 0x200 0x000 ALT1 0x0
#define VF610_PAD_PTE23__SRC_RCON12 0x200 0x000 ALT3 0x0
#define VF610_PAD_PTE23__LCD23 0x200 0x000 ALT4 0x0
#define VF610_PAD_PTE24__GPIO_129 0x204 0x000 ALT0 0x0
#define VF610_PAD_PTE24__DCU0_B3 0x204 0x000 ALT1 0x0
#define VF610_PAD_PTE24__SRC_RCON13 0x204 0x000 ALT3 0x0
#define VF610_PAD_PTE24__LCD24 0x204 0x000 ALT4 0x0
#define VF610_PAD_PTE25__GPIO_130 0x208 0x000 ALT0 0x0
#define VF610_PAD_PTE25__DCU0_B4 0x208 0x000 ALT1 0x0
#define VF610_PAD_PTE25__SRC_RCON14 0x208 0x000 ALT3 0x0
#define VF610_PAD_PTE25__LCD25 0x208 0x000 ALT4 0x0
#define VF610_PAD_PTE26__GPIO_131 0x20C 0x000 ALT0 0x0
#define VF610_PAD_PTE26__DCU0_B5 0x20C 0x000 ALT1 0x0
#define VF610_PAD_PTE26__SRC_RCON15 0x20C 0x000 ALT3 0x0
#define VF610_PAD_PTE26__LCD26 0x20C 0x000 ALT4 0x0
#define VF610_PAD_PTE27__GPIO_132 0x210 0x000 ALT0 0x0
#define VF610_PAD_PTE27__DCU0_B6 0x210 0x000 ALT1 0x0
#define VF610_PAD_PTE27__SRC_RCON16 0x210 0x000 ALT3 0x0
#define VF610_PAD_PTE27__LCD27 0x210 0x000 ALT4 0x0
#define VF610_PAD_PTE27__I2C1_SCL 0x210 0x344 ALT5 0x3
#define VF610_PAD_PTE28__GPIO_133 0x214 0x000 ALT0 0x0
#define VF610_PAD_PTE28__DCU0_B7 0x214 0x000 ALT1 0x0
#define VF610_PAD_PTE28__SRC_RCON17 0x214 0x000 ALT3 0x0
#define VF610_PAD_PTE28__LCD28 0x214 0x000 ALT4 0x0
#define VF610_PAD_PTE28__I2C1_SDA 0x214 0x348 ALT5 0x3
#define VF610_PAD_PTE28__EWM_OUT 0x214 0x000 ALT7 0x0
#define VF610_PAD_PTA7__GPIO_134 0x218 0x000 ALT0 0x0
#define VF610_PAD_PTA7__VIU_PIX_CLK 0x218 0x3AC ALT1 0x1
#endif

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arch/arm/boot/dts/vf610-twr.dts Normal file
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/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
/dts-v1/;
#include "vf610.dtsi"
/ {
model = "VF610 Tower Board";
compatible = "fsl,vf610-twr", "fsl,vf610";
chosen {
bootargs = "console=ttyLP1,115200";
};
memory {
reg = <0x80000000 0x8000000>;
};
clocks {
audio_ext {
compatible = "fixed-clock";
clock-frequency = <24576000>;
};
enet_ext {
compatible = "fixed-clock";
clock-frequency = <50000000>;
};
};
};
&fec0 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec0_1>;
status = "okay";
};
&fec1 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1_1>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_1>;
status = "okay";
};

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/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include "skeleton.dtsi"
#include "vf610-pinfunc.h"
#include <dt-bindings/clock/vf610-clock.h>
/ {
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
serial5 = &uart5;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a5";
device_type = "cpu";
reg = <0x0>;
next-level-cache = <&L2>;
};
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
sxosc {
compatible = "fixed-clock";
clock-frequency = <32768>;
};
fxosc {
compatible = "fixed-clock";
clock-frequency = <24000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
ranges;
aips0: aips-bus@40000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
reg = <0x40000000 0x70000>;
ranges;
intc: interrupt-controller@40002000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
reg = <0x40003000 0x1000>,
<0x40002100 0x100>;
};
L2: l2-cache@40006000 {
compatible = "arm,pl310-cache";
reg = <0x40006000 0x1000>;
cache-unified;
cache-level = <2>;
arm,data-latency = <1 1 1>;
arm,tag-latency = <2 2 2>;
};
uart0: serial@40027000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40027000 0x1000>;
interrupts = <0 61 0x00>;
clocks = <&clks VF610_CLK_UART0>;
clock-names = "ipg";
status = "disabled";
};
uart1: serial@40028000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40028000 0x1000>;
interrupts = <0 62 0x04>;
clocks = <&clks VF610_CLK_UART1>;
clock-names = "ipg";
status = "disabled";
};
uart2: serial@40029000 {
compatible = "fsl,vf610-lpuart";
reg = <0x40029000 0x1000>;
interrupts = <0 63 0x04>;
clocks = <&clks VF610_CLK_UART2>;
clock-names = "ipg";
status = "disabled";
};
uart3: serial@4002a000 {
compatible = "fsl,vf610-lpuart";
reg = <0x4002a000 0x1000>;
interrupts = <0 64 0x04>;
clocks = <&clks VF610_CLK_UART3>;
clock-names = "ipg";
status = "disabled";
};
sai2: sai@40031000 {
compatible = "fsl,vf610-sai";
reg = <0x40031000 0x1000>;
interrupts = <0 86 0x04>;
clocks = <&clks VF610_CLK_SAI2>;
clock-names = "sai";
status = "disabled";
};
pit: pit@40037000 {
compatible = "fsl,vf610-pit";
reg = <0x40037000 0x1000>;
interrupts = <0 39 0x04>;
clocks = <&clks VF610_CLK_PIT>;
clock-names = "pit";
};
wdog@4003e000 {
compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
reg = <0x4003e000 0x1000>;
clocks = <&clks VF610_CLK_WDT>;
clock-names = "wdog";
};
qspi0: quadspi@40044000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-qspi";
reg = <0x40044000 0x1000>;
interrupts = <0 24 0x04>;
clocks = <&clks VF610_CLK_QSPI0_EN>,
<&clks VF610_CLK_QSPI0>;
clock-names = "qspi_en", "qspi";
status = "disabled";
};
iomuxc: iomuxc@40048000 {
compatible = "fsl,vf610-iomuxc";
reg = <0x40048000 0x1000>;
#gpio-range-cells = <3>;
/* functions and groups pins */
dcu0 {
pinctrl_dcu0_1: dcu0grp_1 {
fsl,pins = <
VF610_PAD_PTB8__GPIO_30 0x42
VF610_PAD_PTE0__DCU0_HSYNC 0x42
VF610_PAD_PTE1__DCU0_VSYNC 0x42
VF610_PAD_PTE2__DCU0_PCLK 0x42
VF610_PAD_PTE4__DCU0_DE 0x42
VF610_PAD_PTE5__DCU0_R0 0x42
VF610_PAD_PTE6__DCU0_R1 0x42
VF610_PAD_PTE7__DCU0_R2 0x42
VF610_PAD_PTE8__DCU0_R3 0x42
VF610_PAD_PTE9__DCU0_R4 0x42
VF610_PAD_PTE10__DCU0_R5 0x42
VF610_PAD_PTE11__DCU0_R6 0x42
VF610_PAD_PTE12__DCU0_R7 0x42
VF610_PAD_PTE13__DCU0_G0 0x42
VF610_PAD_PTE14__DCU0_G1 0x42
VF610_PAD_PTE15__DCU0_G2 0x42
VF610_PAD_PTE16__DCU0_G3 0x42
VF610_PAD_PTE17__DCU0_G4 0x42
VF610_PAD_PTE18__DCU0_G5 0x42
VF610_PAD_PTE19__DCU0_G6 0x42
VF610_PAD_PTE20__DCU0_G7 0x42
VF610_PAD_PTE21__DCU0_B0 0x42
VF610_PAD_PTE22__DCU0_B1 0x42
VF610_PAD_PTE23__DCU0_B2 0x42
VF610_PAD_PTE24__DCU0_B3 0x42
VF610_PAD_PTE25__DCU0_B4 0x42
VF610_PAD_PTE26__DCU0_B5 0x42
VF610_PAD_PTE27__DCU0_B6 0x42
VF610_PAD_PTE28__DCU0_B7 0x42
>;
};
};
dspi0 {
pinctrl_dspi0_1: dspi0grp_1 {
fsl,pins = <
VF610_PAD_PTB19__DSPI0_CS0 0x1182
VF610_PAD_PTB20__DSPI0_SIN 0x1181
VF610_PAD_PTB21__DSPI0_SOUT 0x1182
VF610_PAD_PTB22__DSPI0_SCK 0x1182
>;
};
};
esdhc1 {
pinctrl_esdhc1_1: esdhc1grp_1 {
fsl,pins = <
VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
VF610_PAD_PTA7__GPIO_134 0x219d
>;
};
};
fec0 {
pinctrl_fec0_1: fec0grp_1 {
fsl,pins = <
VF610_PAD_PTA6__RMII_CLKIN 0x30d1
VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3
VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
>;
};
};
fec1 {
pinctrl_fec1_1: fec1grp_1 {
fsl,pins = <
VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
>;
};
};
i2c0 {
pinctrl_i2c0_1: i2c0grp_1 {
fsl,pins = <
VF610_PAD_PTB14__I2C0_SCL 0x30d3
VF610_PAD_PTB15__I2C0_SDA 0x30d3
>;
};
};
pwm0 {
pinctrl_pwm0_1: pwm0grp_1 {
fsl,pins = <
VF610_PAD_PTB0__FTM0_CH0 0x1582
VF610_PAD_PTB1__FTM0_CH1 0x1582
VF610_PAD_PTB2__FTM0_CH2 0x1582
VF610_PAD_PTB3__FTM0_CH3 0x1582
VF610_PAD_PTB6__FTM0_CH6 0x1582
VF610_PAD_PTB7__FTM0_CH7 0x1582
>;
};
};
qspi0 {
pinctrl_qspi0_1: qspi0grp_1 {
fsl,pins = <
VF610_PAD_PTD0__QSPI0_A_QSCK 0x307b
VF610_PAD_PTD1__QSPI0_A_CS0 0x307f
VF610_PAD_PTD2__QSPI0_A_DATA3 0x3073
VF610_PAD_PTD3__QSPI0_A_DATA2 0x3073
VF610_PAD_PTD4__QSPI0_A_DATA1 0x3073
VF610_PAD_PTD5__QSPI0_A_DATA0 0x307b
VF610_PAD_PTD7__QSPI0_B_QSCK 0x307b
VF610_PAD_PTD8__QSPI0_B_CS0 0x307f
VF610_PAD_PTD9__QSPI0_B_DATA3 0x3073
VF610_PAD_PTD10__QSPI0_B_DATA2 0x3073
VF610_PAD_PTD11__QSPI0_B_DATA1 0x3073
VF610_PAD_PTD12__QSPI0_B_DATA0 0x307b
>;
};
};
sai2 {
pinctrl_sai2_1: sai2grp_1 {
fsl,pins = <
VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed
VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee
VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed
VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed
VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed
VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed
VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
>;
};
};
uart1 {
pinctrl_uart1_1: uart1grp_1 {
fsl,pins = <
VF610_PAD_PTB4__UART1_TX 0x21a2
VF610_PAD_PTB5__UART1_RX 0x21a1
>;
};
};
usbvbus {
pinctrl_usbvbus_1: usbvbusgrp_1 {
fsl,pins = <
VF610_PAD_PTA24__USB1_VBUS_EN 0x219c
VF610_PAD_PTA16__USB0_VBUS_EN 0x219c
>;
};
};
};
gpio1: gpio@40049000 {
compatible = "fsl,vf610-gpio";
reg = <0x40049000 0x1000 0x400ff000 0x40>;
interrupts = <0 107 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 0 32>;
};
gpio2: gpio@4004a000 {
compatible = "fsl,vf610-gpio";
reg = <0x4004a000 0x1000 0x400ff040 0x40>;
interrupts = <0 108 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 32 32>;
};
gpio3: gpio@4004b000 {
compatible = "fsl,vf610-gpio";
reg = <0x4004b000 0x1000 0x400ff080 0x40>;
interrupts = <0 109 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 64 32>;
};
gpio4: gpio@4004c000 {
compatible = "fsl,vf610-gpio";
reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
interrupts = <0 110 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 96 32>;
};
gpio5: gpio@4004d000 {
compatible = "fsl,vf610-gpio";
reg = <0x4004d000 0x1000 0x400ff100 0x40>;
interrupts = <0 111 0x04>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&iomuxc 0 128 7>;
};
anatop@40050000 {
compatible = "fsl,vf610-anatop";
reg = <0x40050000 0x1000>;
};
i2c0: i2c@40066000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,vf610-i2c";
reg = <0x40066000 0x1000>;
interrupts =<0 71 0x04>;
clocks = <&clks VF610_CLK_I2C0>;
clock-names = "ipg";
status = "disabled";
};
clks: ccm@4006b000 {
compatible = "fsl,vf610-ccm";
reg = <0x4006b000 0x1000>;
#clock-cells = <1>;
};
};
aips1: aips-bus@40080000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40080000 0x80000>;
ranges;
uart4: serial@400a9000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400a9000 0x1000>;
interrupts = <0 65 0x04>;
clocks = <&clks VF610_CLK_UART4>;
clock-names = "ipg";
status = "disabled";
};
uart5: serial@400aa000 {
compatible = "fsl,vf610-lpuart";
reg = <0x400aa000 0x1000>;
interrupts = <0 66 0x04>;
clocks = <&clks VF610_CLK_UART5>;
clock-names = "ipg";
status = "disabled";
};
fec0: ethernet@400d0000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d0000 0x1000>;
interrupts = <0 78 0x04>;
clocks = <&clks VF610_CLK_ENET>,
<&clks VF610_CLK_ENET>,
<&clks VF610_CLK_ENET>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
fec1: ethernet@400d1000 {
compatible = "fsl,mvf600-fec";
reg = <0x400d1000 0x1000>;
interrupts = <0 79 0x04>;
clocks = <&clks VF610_CLK_ENET>,
<&clks VF610_CLK_ENET>,
<&clks VF610_CLK_ENET>;
clock-names = "ipg", "ahb", "ptp";
status = "disabled";
};
};
};
};

2
arch/arm/mach-imx/clk-imx51-imx53.c
View File

@ -327,8 +327,6 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
clk_register_clkdev(clk[cpu_podf], NULL, "cpufreq-cpu0.0");
clk_register_clkdev(clk[iim_gate], "iim", NULL);

16
arch/arm/mach-imx/mach-imx53.c
View File

@ -24,26 +24,10 @@
#include "hardware.h"
#include "mx53.h"
static void __init imx53_qsb_init(void)
{
struct clk *clk;
clk = clk_get_sys(NULL, "ssi_ext1");
if (IS_ERR(clk)) {
pr_err("failed to get clk ssi_ext1\n");
return;
}
clk_register_clkdev(clk, NULL, "0-000a");
}
static void __init imx53_dt_init(void)
{
mxc_arch_reset_init_dt();
if (of_machine_is_compatible("fsl,imx53-qsb"))
imx53_qsb_init();
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}

9
drivers/bus/Kconfig
View File

@ -4,6 +4,15 @@
menu "Bus devices"
config IMX_WEIM
bool "Freescale EIM DRIVER"
depends on ARCH_MXC
help
Driver for i.MX6 WEIM controller.
The WEIM(Wireless External Interface Module) works like a bus.
You can attach many different devices on it, such as NOR, onenand.
But now, we only support the Parallel NOR.
config MVEBU_MBUS
bool
depends on PLAT_ORION

1
drivers/bus/Makefile
View File

@ -2,6 +2,7 @@
# Makefile for the bus drivers.
#
obj-$(CONFIG_IMX_WEIM) += imx-weim.o
obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o

138
drivers/bus/imx-weim.c Normal file
View File

@ -0,0 +1,138 @@
/*
* EIM driver for Freescale's i.MX chips
*
* Copyright (C) 2013 Freescale Semiconductor, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/of_device.h>
struct imx_weim {
void __iomem *base;
struct clk *clk;
};
static const struct of_device_id weim_id_table[] = {
{ .compatible = "fsl,imx6q-weim", },
{}
};
MODULE_DEVICE_TABLE(of, weim_id_table);
#define CS_TIMING_LEN 6
#define CS_REG_RANGE 0x18
/* Parse and set the timing for this device. */
static int
weim_timing_setup(struct platform_device *pdev, struct device_node *np)
{
struct imx_weim *weim = platform_get_drvdata(pdev);
u32 value[CS_TIMING_LEN];
u32 cs_idx;
int ret;
int i;
/* get the CS index from this child node's "reg" property. */
ret = of_property_read_u32(np, "reg", &cs_idx);
if (ret)
return ret;
/* The weim has four chip selects. */
if (cs_idx > 3)
return -EINVAL;
ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
value, CS_TIMING_LEN);
if (ret)
return ret;
/* set the timing for WEIM */
for (i = 0; i < CS_TIMING_LEN; i++)
writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4);
return 0;
}
static int weim_parse_dt(struct platform_device *pdev)
{
struct device_node *child;
int ret;
for_each_child_of_node(pdev->dev.of_node, child) {
if (!child->name)
continue;
ret = weim_timing_setup(pdev, child);
if (ret) {
dev_err(&pdev->dev, "%s set timing failed.\n",
child->full_name);
return ret;
}
}
ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
if (ret)
dev_err(&pdev->dev, "%s fail to create devices.\n",
pdev->dev.of_node->full_name);
return ret;
}
static int weim_probe(struct platform_device *pdev)
{
struct imx_weim *weim;
struct resource *res;
int ret = -EINVAL;
weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL);
if (!weim) {
ret = -ENOMEM;
goto weim_err;
}
platform_set_drvdata(pdev, weim);
/* get the resource */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
weim->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(weim->base)) {
ret = PTR_ERR(weim->base);
goto weim_err;
}
/* get the clock */
weim->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(weim->clk))
goto weim_err;
ret = clk_prepare_enable(weim->clk);
if (ret)
goto weim_err;
/* parse the device node */
ret = weim_parse_dt(pdev);
if (ret) {
clk_disable_unprepare(weim->clk);
goto weim_err;
}
dev_info(&pdev->dev, "WEIM driver registered.\n");
return 0;
weim_err:
return ret;
}
static struct platform_driver weim_driver = {
.driver = {
.name = "imx-weim",
.of_match_table = weim_id_table,
},
.probe = weim_probe,
};
module_platform_driver(weim_driver);
MODULE_AUTHOR("Freescale Semiconductor Inc.");
MODULE_DESCRIPTION("i.MX EIM Controller Driver");
MODULE_LICENSE("GPL");