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drm/amdgpu: enable psp support for vangogh
This patch is to enable psp support for vangogh Signed-off-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
5120cb5409
commit
ed3b735332
4 changed files with 9 additions and 2 deletions
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@ -100,6 +100,7 @@ static int psp_early_init(void *handle)
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case CHIP_NAVI12:
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case CHIP_NAVI12:
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case CHIP_SIENNA_CICHLID:
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case CHIP_SIENNA_CICHLID:
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case CHIP_NAVY_FLOUNDER:
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case CHIP_NAVY_FLOUNDER:
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case CHIP_VANGOGH:
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psp_v11_0_set_psp_funcs(psp);
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psp_v11_0_set_psp_funcs(psp);
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psp->autoload_supported = true;
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psp->autoload_supported = true;
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break;
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break;
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@ -391,12 +391,11 @@ amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type)
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case CHIP_NAVI12:
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case CHIP_NAVI12:
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case CHIP_SIENNA_CICHLID:
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case CHIP_SIENNA_CICHLID:
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case CHIP_NAVY_FLOUNDER:
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case CHIP_NAVY_FLOUNDER:
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case CHIP_VANGOGH:
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if (!load_type)
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if (!load_type)
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return AMDGPU_FW_LOAD_DIRECT;
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return AMDGPU_FW_LOAD_DIRECT;
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else
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else
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return AMDGPU_FW_LOAD_PSP;
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return AMDGPU_FW_LOAD_PSP;
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case CHIP_VANGOGH:
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return AMDGPU_FW_LOAD_DIRECT;
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default:
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default:
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DRM_ERROR("Unknown firmware load type\n");
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DRM_ERROR("Unknown firmware load type\n");
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}
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}
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@ -609,6 +609,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
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amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
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amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
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amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
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amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
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amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
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if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
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amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
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amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
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amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
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if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
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if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
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amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
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amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
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@ -59,6 +59,8 @@ MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
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MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
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MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
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MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
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MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
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MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
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MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
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MODULE_FIRMWARE("amdgpu/vangogh_asd.bin");
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MODULE_FIRMWARE("amdgpu/vangogh_toc.bin");
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/* address block */
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/* address block */
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#define smnMP1_FIRMWARE_FLAGS 0x3010024
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#define smnMP1_FIRMWARE_FLAGS 0x3010024
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@ -105,6 +107,9 @@ static int psp_v11_0_init_microcode(struct psp_context *psp)
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case CHIP_NAVY_FLOUNDER:
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case CHIP_NAVY_FLOUNDER:
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chip_name = "navy_flounder";
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chip_name = "navy_flounder";
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break;
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break;
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case CHIP_VANGOGH:
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chip_name = "vangogh";
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break;
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default:
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default:
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BUG();
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BUG();
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}
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}
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