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drivers/amdgpu: Use 'true/false' for bool typed variables
Found-by: Coccinelle Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net> Reviewed-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
9c3578af81
commit
ed5121a3d8
5 changed files with 25 additions and 25 deletions
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@ -425,7 +425,7 @@ static int cz_dpm_init(struct amdgpu_device *adev)
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pi->mgcg_cgtt_local1 = 0x0;
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pi->clock_slow_down_step = 25000;
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pi->skip_clock_slow_down = 1;
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pi->enable_nb_ps_policy = 0;
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pi->enable_nb_ps_policy = false;
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pi->caps_power_containment = true;
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pi->caps_cac = true;
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pi->didt_enabled = false;
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@ -176,7 +176,7 @@ static int pp_hw_fini(void *handle)
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static bool pp_is_idle(void *handle)
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{
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return 0;
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return false;
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}
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static int pp_wait_for_idle(void *handle)
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@ -698,7 +698,7 @@ static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
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if (0 == result) {
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struct cgs_system_info sys_info = {0};
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data->is_tlu_enabled = 0;
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data->is_tlu_enabled = false;
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hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
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FIJI_MAX_HARDWARE_POWERLEVELS;
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hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
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@ -1450,7 +1450,7 @@ static void fiji_setup_pcie_table_entry(
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{
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dpm_table->dpm_levels[index].value = pcie_gen;
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dpm_table->dpm_levels[index].param1 = pcie_lanes;
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dpm_table->dpm_levels[index].enabled = 1;
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dpm_table->dpm_levels[index].enabled = true;
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}
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static int fiji_setup_default_pcie_table(struct pp_hwmgr *hwmgr)
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@ -3261,7 +3261,7 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
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if (0 == result) {
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struct cgs_system_info sys_info = {0};
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data->is_tlu_enabled = 0;
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data->is_tlu_enabled = false;
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hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
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POLARIS10_MAX_HARDWARE_POWERLEVELS;
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@ -774,7 +774,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
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uint32_t tmp;
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int result;
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bool error = 0;
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bool error = false;
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result = tonga_read_smc_sram_dword(hwmgr->smumgr,
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SMU72_FIRMWARE_HEADER_LOCATION +
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@ -933,11 +933,11 @@ int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr)
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{
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tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
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data->uvd_power_gated = 0;
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data->vce_power_gated = 0;
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data->samu_power_gated = 0;
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data->acp_power_gated = 0;
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data->pg_acp_init = 1;
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data->uvd_power_gated = false;
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data->vce_power_gated = false;
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data->samu_power_gated = false;
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data->acp_power_gated = false;
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data->pg_acp_init = true;
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return 0;
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}
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@ -991,7 +991,7 @@ static int tonga_trim_voltage_table(struct pp_hwmgr *hwmgr,
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{
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uint32_t table_size, i, j;
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uint16_t vvalue;
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bool bVoltageFound = 0;
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bool bVoltageFound = false;
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pp_atomctrl_voltage_table *table;
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PP_ASSERT_WITH_CODE((NULL != voltage_table), "Voltage Table empty.", return -1;);
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@ -1007,11 +1007,11 @@ static int tonga_trim_voltage_table(struct pp_hwmgr *hwmgr,
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for (i = 0; i < voltage_table->count; i++) {
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vvalue = voltage_table->entries[i].value;
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bVoltageFound = 0;
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bVoltageFound = false;
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for (j = 0; j < table->count; j++) {
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if (vvalue == table->entries[j].value) {
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bVoltageFound = 1;
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bVoltageFound = true;
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break;
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}
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}
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@ -2705,7 +2705,7 @@ static int tonga_reset_single_dpm_table(
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dpm_table->count = count;
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for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) {
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dpm_table->dpm_levels[i].enabled = 0;
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dpm_table->dpm_levels[i].enabled = false;
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}
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return 0;
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@ -2718,7 +2718,7 @@ static void tonga_setup_pcie_table_entry(
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{
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dpm_table->dpm_levels[index].value = pcie_gen;
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dpm_table->dpm_levels[index].param1 = pcie_lanes;
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dpm_table->dpm_levels[index].enabled = 1;
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dpm_table->dpm_levels[index].enabled = true;
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}
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static int tonga_setup_default_pcie_tables(struct pp_hwmgr *hwmgr)
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@ -2828,7 +2828,7 @@ static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
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allowed_vdd_sclk_table->entries[i].clk) {
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data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
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allowed_vdd_sclk_table->entries[i].clk;
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data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; to do */
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data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = true; /*(i==0) ? 1 : 0; to do */
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data->dpm_table.sclk_table.count++;
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}
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}
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@ -2842,7 +2842,7 @@ static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
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allowed_vdd_mclk_table->entries[i].clk) {
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data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
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allowed_vdd_mclk_table->entries[i].clk;
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data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; */
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data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = true; /*(i==0) ? 1 : 0; */
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data->dpm_table.mclk_table.count++;
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}
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}
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@ -3741,7 +3741,7 @@ uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
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bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
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{
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bool result = 1;
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bool result = true;
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switch (inReg) {
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case mmMC_SEQ_RAS_TIMING:
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@ -3825,7 +3825,7 @@ bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
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break;
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default:
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result = 0;
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result = false;
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break;
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}
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@ -4449,7 +4449,7 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
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hwmgr->backend = data;
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data->dll_defaule_on = 0;
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data->dll_defaule_on = false;
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data->sram_end = SMC_RAM_END;
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data->activity_target[0] = PPTONGA_TARGETACTIVITY_DFLT;
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@ -4555,13 +4555,13 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
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/* ULV Support*/
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ulv = &(data->ulv);
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ulv->ulv_supported = 0;
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ulv->ulv_supported = false;
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/* Initalize Dynamic State Adjustment Rule Settings*/
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result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
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if (result)
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printk(KERN_ERR "[ powerplay ] tonga_initializa_dynamic_state_adjustment_rule_settings failed!\n");
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data->uvd_enabled = 0;
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data->uvd_enabled = false;
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table = &(data->smc_state_table);
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@ -4608,7 +4608,7 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_SMU7);
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data->vddc_phase_shed_control = 0;
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data->vddc_phase_shed_control = false;
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phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_UVDPowerGating);
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@ -4627,7 +4627,7 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
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}
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if (0 == result) {
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data->is_tlu_enabled = 0;
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data->is_tlu_enabled = false;
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hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
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TONGA_MAX_HARDWARE_POWERLEVELS;
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hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
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