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Code Issues Releases Wiki Activity

drivers/amdgpu: Use 'true/false' for bool typed variables

Browse source 
Found-by: Coccinelle
Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Edward O'Callaghan 2016-07-12 10:17:52 +10:00 committed by Alex Deucher
parent 9c3578af81
commit ed5121a3d8
5 changed files with 25 additions and 25 deletions
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2
drivers/gpu/drm/amd/amdgpu/cz_dpm.c
View file

@ -425,7 +425,7 @@ static int cz_dpm_init(struct amdgpu_device *adev)
pi->mgcg_cgtt_local1 = 0x0;
pi->clock_slow_down_step = 25000;
pi->skip_clock_slow_down = 1;
pi->enable_nb_ps_policy = 0;
pi->enable_nb_ps_policy = false;
pi->caps_power_containment = true;
pi->caps_cac = true;
pi->didt_enabled = false;

2
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
View file

@ -176,7 +176,7 @@ static int pp_hw_fini(void *handle)
static bool pp_is_idle(void *handle)
{
return 0;
return false;
}
static int pp_wait_for_idle(void *handle)

4
drivers/gpu/drm/amd/powerplay/hwmgr/fiji_hwmgr.c
View file

@ -698,7 +698,7 @@ static int fiji_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
if (0 == result) {
struct cgs_system_info sys_info = {0};
data->is_tlu_enabled = 0;
data->is_tlu_enabled = false;
hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
FIJI_MAX_HARDWARE_POWERLEVELS;
hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
@ -1450,7 +1450,7 @@ static void fiji_setup_pcie_table_entry(
{
dpm_table->dpm_levels[index].value = pcie_gen;
dpm_table->dpm_levels[index].param1 = pcie_lanes;
dpm_table->dpm_levels[index].enabled = 1;
dpm_table->dpm_levels[index].enabled = true;
}
static int fiji_setup_default_pcie_table(struct pp_hwmgr *hwmgr)

2
drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
View file

@ -3261,7 +3261,7 @@ int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
if (0 == result) {
struct cgs_system_info sys_info = {0};
data->is_tlu_enabled = 0;
data->is_tlu_enabled = false;
hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
POLARIS10_MAX_HARDWARE_POWERLEVELS;

40
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_hwmgr.c
View file

@ -774,7 +774,7 @@ int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
uint32_t tmp;
int result;
bool error = 0;
bool error = false;
result = tonga_read_smc_sram_dword(hwmgr->smumgr,
SMU72_FIRMWARE_HEADER_LOCATION +
@ -933,11 +933,11 @@ int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
data->uvd_power_gated = 0;
data->vce_power_gated = 0;
data->samu_power_gated = 0;
data->acp_power_gated = 0;
data->pg_acp_init = 1;
data->uvd_power_gated = false;
data->vce_power_gated = false;
data->samu_power_gated = false;
data->acp_power_gated = false;
data->pg_acp_init = true;
return 0;
}
@ -991,7 +991,7 @@ static int tonga_trim_voltage_table(struct pp_hwmgr *hwmgr,
{
uint32_t table_size, i, j;
uint16_t vvalue;
bool bVoltageFound = 0;
bool bVoltageFound = false;
pp_atomctrl_voltage_table *table;
PP_ASSERT_WITH_CODE((NULL != voltage_table), "Voltage Table empty.", return -1;);
@ -1007,11 +1007,11 @@ static int tonga_trim_voltage_table(struct pp_hwmgr *hwmgr,
for (i = 0; i < voltage_table->count; i++) {
vvalue = voltage_table->entries[i].value;
bVoltageFound = 0;
bVoltageFound = false;
for (j = 0; j < table->count; j++) {
if (vvalue == table->entries[j].value) {
bVoltageFound = 1;
bVoltageFound = true;
break;
}
}
@ -2705,7 +2705,7 @@ static int tonga_reset_single_dpm_table(
dpm_table->count = count;
for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++) {
dpm_table->dpm_levels[i].enabled = 0;
dpm_table->dpm_levels[i].enabled = false;
}
return 0;
@ -2718,7 +2718,7 @@ static void tonga_setup_pcie_table_entry(
{
dpm_table->dpm_levels[index].value = pcie_gen;
dpm_table->dpm_levels[index].param1 = pcie_lanes;
dpm_table->dpm_levels[index].enabled = 1;
dpm_table->dpm_levels[index].enabled = true;
}
static int tonga_setup_default_pcie_tables(struct pp_hwmgr *hwmgr)
@ -2828,7 +2828,7 @@ static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
allowed_vdd_sclk_table->entries[i].clk) {
data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value =
allowed_vdd_sclk_table->entries[i].clk;
data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; to do */
data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = true; /*(i==0) ? 1 : 0; to do */
data->dpm_table.sclk_table.count++;
}
}
@ -2842,7 +2842,7 @@ static int tonga_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
allowed_vdd_mclk_table->entries[i].clk) {
data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].value =
allowed_vdd_mclk_table->entries[i].clk;
data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = 1; /*(i==0) ? 1 : 0; */
data->dpm_table.mclk_table.dpm_levels[data->dpm_table.mclk_table.count].enabled = true; /*(i==0) ? 1 : 0; */
data->dpm_table.mclk_table.count++;
}
}
@ -3741,7 +3741,7 @@ uint8_t tonga_get_memory_modile_index(struct pp_hwmgr *hwmgr)
bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
{
bool result = 1;
bool result = true;
switch (inReg) {
case mmMC_SEQ_RAS_TIMING:
@ -3825,7 +3825,7 @@ bool tonga_check_s0_mc_reg_index(uint16_t inReg, uint16_t *outReg)
break;
default:
result = 0;
result = false;
break;
}
@ -4449,7 +4449,7 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
hwmgr->backend = data;
data->dll_defaule_on = 0;
data->dll_defaule_on = false;
data->sram_end = SMC_RAM_END;
data->activity_target[0] = PPTONGA_TARGETACTIVITY_DFLT;
@ -4555,13 +4555,13 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
/* ULV Support*/
ulv = &(data->ulv);
ulv->ulv_supported = 0;
ulv->ulv_supported = false;
/* Initalize Dynamic State Adjustment Rule Settings*/
result = tonga_initializa_dynamic_state_adjustment_rule_settings(hwmgr);
if (result)
printk(KERN_ERR "[ powerplay ] tonga_initializa_dynamic_state_adjustment_rule_settings failed!\n");
data->uvd_enabled = 0;
data->uvd_enabled = false;
table = &(data->smc_state_table);
@ -4608,7 +4608,7 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SMU7);
data->vddc_phase_shed_control = 0;
data->vddc_phase_shed_control = false;
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_UVDPowerGating);
@ -4627,7 +4627,7 @@ int tonga_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
}
if (0 == result) {
data->is_tlu_enabled = 0;
data->is_tlu_enabled = false;
hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
TONGA_MAX_HARDWARE_POWERLEVELS;
hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;