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drm/amdgpu/pp: fix copy paste typo in smu7_get_pp_table_entry_callback_func_v1

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Should be using PCIELaneLow for the low clock level.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2018-06-28 13:21:12 -05:00
parent 9861023c29
commit ed54d954e5
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
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@ -3183,7 +3183,7 @@ static int smu7_get_pp_table_entry_callback_func_v1(struct pp_hwmgr *hwmgr,
performance_level->pcie_gen = get_pcie_gen_support(data->pcie_gen_cap,
state_entry->ucPCIEGenLow);
performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap,
state_entry->ucPCIELaneHigh);
state_entry->ucPCIELaneLow);
performance_level = &(smu7_power_state->performance_levels
[smu7_power_state->performance_level_count++]);