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synced 2024-10-06 08:46:46 +00:00
MIPS: MT: Remove obsolete cache flush repeat code
In much the same vein as commitac41f9c462("MIPS: Remove a temporary hack for debugging cache flushes in SMTC configuration") and commiteb75ecb113("MIPS: MT: Remove unused MT single-threaded cache flush code"), remove the long obsolete ndflush & niflush command line arguments which provided a hack that should not be useful outside of debug sessions performed long ago. Signed-off-by: Paul Burton <paul.burton@mips.com>
This commit is contained in:
Paul Burton
parent
eb75ecb113
commit
edaa978e52
2 changed files with 0 additions and 112 deletions
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@ -48,58 +48,14 @@ extern void (*r4k_blast_icache)(void);
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: \
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: "i" (op), "R" (*(unsigned char *)(addr)))
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#ifdef CONFIG_MIPS_MT
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#define __iflush_prologue \
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unsigned long redundance; \
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extern int mt_n_iflushes; \
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for (redundance = 0; redundance < mt_n_iflushes; redundance++) {
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#define __iflush_epilogue \
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}
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#define __dflush_prologue \
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unsigned long redundance; \
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extern int mt_n_dflushes; \
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for (redundance = 0; redundance < mt_n_dflushes; redundance++) {
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#define __dflush_epilogue \
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}
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#define __inv_dflush_prologue __dflush_prologue
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#define __inv_dflush_epilogue __dflush_epilogue
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#define __sflush_prologue {
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#define __sflush_epilogue }
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#define __inv_sflush_prologue __sflush_prologue
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#define __inv_sflush_epilogue __sflush_epilogue
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#else /* CONFIG_MIPS_MT */
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#define __iflush_prologue {
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#define __iflush_epilogue }
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#define __dflush_prologue {
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#define __dflush_epilogue }
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#define __inv_dflush_prologue {
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#define __inv_dflush_epilogue }
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#define __sflush_prologue {
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#define __sflush_epilogue }
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#define __inv_sflush_prologue {
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#define __inv_sflush_epilogue }
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#endif /* CONFIG_MIPS_MT */
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static inline void flush_icache_line_indexed(unsigned long addr)
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{
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__iflush_prologue
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cache_op(Index_Invalidate_I, addr);
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__iflush_epilogue
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}
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static inline void flush_dcache_line_indexed(unsigned long addr)
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{
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__dflush_prologue
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cache_op(Index_Writeback_Inv_D, addr);
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__dflush_epilogue
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}
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static inline void flush_scache_line_indexed(unsigned long addr)
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@ -109,7 +65,6 @@ static inline void flush_scache_line_indexed(unsigned long addr)
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static inline void flush_icache_line(unsigned long addr)
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{
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__iflush_prologue
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switch (boot_cpu_type()) {
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case CPU_LOONGSON2:
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cache_op(Hit_Invalidate_I_Loongson2, addr);
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@ -119,21 +74,16 @@ static inline void flush_icache_line(unsigned long addr)
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cache_op(Hit_Invalidate_I, addr);
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break;
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}
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__iflush_epilogue
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}
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static inline void flush_dcache_line(unsigned long addr)
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{
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__dflush_prologue
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cache_op(Hit_Writeback_Inv_D, addr);
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__dflush_epilogue
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}
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static inline void invalidate_dcache_line(unsigned long addr)
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{
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__dflush_prologue
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cache_op(Hit_Invalidate_D, addr);
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__dflush_epilogue
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}
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static inline void invalidate_scache_line(unsigned long addr)
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@ -586,13 +536,9 @@ static inline void extra##blast_##pfx##cache##lsize(void) \
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current_cpu_data.desc.waybit; \
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unsigned long ws, addr; \
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\
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__##pfx##flush_prologue \
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\
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (addr = start; addr < end; addr += lsize * 32) \
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cache##lsize##_unroll32(addr|ws, indexop); \
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\
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__##pfx##flush_epilogue \
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} \
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\
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static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \
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@ -600,14 +546,10 @@ static inline void extra##blast_##pfx##cache##lsize##_page(unsigned long page) \
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unsigned long start = page; \
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unsigned long end = page + PAGE_SIZE; \
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\
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__##pfx##flush_prologue \
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\
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do { \
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cache##lsize##_unroll32(start, hitop); \
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start += lsize * 32; \
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} while (start < end); \
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\
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__##pfx##flush_epilogue \
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} \
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\
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static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
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@ -620,13 +562,9 @@ static inline void extra##blast_##pfx##cache##lsize##_page_indexed(unsigned long
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current_cpu_data.desc.waybit; \
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unsigned long ws, addr; \
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\
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__##pfx##flush_prologue \
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\
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for (ws = 0; ws < ws_end; ws += ws_inc) \
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for (addr = start; addr < end; addr += lsize * 32) \
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cache##lsize##_unroll32(addr|ws, indexop); \
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\
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__##pfx##flush_epilogue \
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}
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__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
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@ -656,14 +594,10 @@ static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
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unsigned long start = page; \
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unsigned long end = page + PAGE_SIZE; \
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\
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__##pfx##flush_prologue \
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\
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do { \
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cache##lsize##_unroll32_user(start, hitop); \
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start += lsize * 32; \
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} while (start < end); \
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\
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__##pfx##flush_epilogue \
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}
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__BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
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@ -685,16 +619,12 @@ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start,
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unsigned long addr = start & ~(lsize - 1); \
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unsigned long aend = (end - 1) & ~(lsize - 1); \
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\
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__##pfx##flush_prologue \
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\
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while (1) { \
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prot##cache_op(hitop, addr); \
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if (addr == aend) \
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break; \
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addr += lsize; \
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} \
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\
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__##pfx##flush_epilogue \
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}
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#ifndef CONFIG_EVA
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@ -712,8 +642,6 @@ static inline void protected_blast_##pfx##cache##_range(unsigned long start,\
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unsigned long addr = start & ~(lsize - 1); \
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unsigned long aend = (end - 1) & ~(lsize - 1); \
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\
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__##pfx##flush_prologue \
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\
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if (!uaccess_kernel()) { \
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while (1) { \
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protected_cachee_op(hitop, addr); \
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@ -730,7 +658,6 @@ static inline void protected_blast_##pfx##cache##_range(unsigned long start,\
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} \
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\
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} \
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__##pfx##flush_epilogue \
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}
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__BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
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@ -154,24 +154,6 @@ static int __init config7_set(char *str)
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}
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__setup("config7=", config7_set);
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/* Experimental cache flush control parameters that should go away some day */
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int mt_n_iflushes = 1;
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int mt_n_dflushes = 1;
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static int __init niflush(char *s)
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{
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get_option(&s, &mt_n_iflushes);
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return 1;
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}
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__setup("niflush=", niflush);
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static int __init ndflush(char *s)
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{
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get_option(&s, &mt_n_dflushes);
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return 1;
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}
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__setup("ndflush=", ndflush);
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static unsigned int itc_base;
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static int __init set_itc_base(char *str)
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@ -216,12 +198,6 @@ void mips_mt_set_cpuoptions(void)
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printk("Config7: 0x%08x\n", read_c0_config7());
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}
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/* Report Cache management debug options */
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if (mt_n_iflushes != 1)
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printk("I-Cache Flushes Repeated %d times\n", mt_n_iflushes);
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if (mt_n_dflushes != 1)
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printk("D-Cache Flushes Repeated %d times\n", mt_n_dflushes);
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if (itc_base != 0) {
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/*
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* Configure ITC mapping. This code is very
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@ -263,21 +239,6 @@ void mips_mt_set_cpuoptions(void)
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}
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}
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/*
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* Function to protect cache flushes from concurrent execution
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* depends on MP software model chosen.
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*/
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void mt_cflush_lockdown(void)
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{
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/* FILL IN VSMP and AP/SP VERSIONS HERE */
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}
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void mt_cflush_release(void)
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{
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/* FILL IN VSMP and AP/SP VERSIONS HERE */
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}
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struct class *mt_class;
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static int __init mt_init(void)
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