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ARM: exynos: use private samsung_cpu_id copy 

The only part of plat-samsung that is shared with arch-exynos
is the CPU identification code.

Having a separate exynos_cpu_id variable makes the two completely
independent and is actually a bit less code in total.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20200806182059.2431-14-krzk@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Arnd Bergmann 2020-08-06 20:20:31 +02:00 committed by Krzysztof Kozlowski
parent b3a775127d
commit edaff7e1c6
8 changed files with 25 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/mach-exynos/common.h
View File

@ -24,12 +24,12 @@
#define EXYNOS5800_SOC_ID 0xE5422000
#define EXYNOS5_SOC_MASK 0xFFFFF000
extern unsigned long samsung_cpu_id;
extern unsigned long exynos_cpu_id;
#define IS_SAMSUNG_CPU(name, id, mask) \
static inline int is_samsung_##name(void) \
{ \
return ((samsung_cpu_id & mask) == (id & mask)); \
return ((exynos_cpu_id & mask) == (id & mask)); \
}
IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK)
@ -147,7 +147,7 @@ extern struct cpuidle_exynos_data cpuidle_coupled_exynos_data;
extern void exynos_set_delayed_reset_assertion(bool enable);
extern unsigned int samsung_rev(void);
extern unsigned int exynos_rev(void);
extern void exynos_core_restart(u32 core_id);
extern int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr);
extern int exynos_get_boot_addr(u32 core_id, unsigned long *boot_addr);

21
arch/arm/mach-exynos/exynos.c
View File

@ -19,11 +19,12 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <mach/map.h>
#include <plat/cpu.h>
#include "common.h"
#define S3C_ADDR_BASE 0xF6000000
#define S3C_ADDR(x) ((void __iomem __force *)S3C_ADDR_BASE + (x))
#define S5P_VA_CHIPID S3C_ADDR(0x02000000)
static struct platform_device exynos_cpuidle = {
.name = "exynos_cpuidle",
#ifdef CONFIG_ARM_EXYNOS_CPUIDLE
@ -36,6 +37,14 @@ void __iomem *sysram_base_addr __ro_after_init;
phys_addr_t sysram_base_phys __ro_after_init;
void __iomem *sysram_ns_base_addr __ro_after_init;
unsigned long exynos_cpu_id;
static unsigned int exynos_cpu_rev;
unsigned int exynos_rev(void)
{
return exynos_cpu_rev;
}
void __init exynos_sysram_init(void)
{
struct device_node *node;
@ -86,7 +95,11 @@ static void __init exynos_init_io(void)
of_scan_flat_dt(exynos_fdt_map_chipid, NULL);
/* detect cpu id and rev. */
s5p_init_cpu(S5P_VA_CHIPID);
exynos_cpu_id = readl_relaxed(S5P_VA_CHIPID);
exynos_cpu_rev = exynos_cpu_id & 0xFF;
pr_info("Samsung CPU ID: 0x%08lx\n", exynos_cpu_id);
}
/*

18
arch/arm/mach-exynos/include/mach/map.h
View File

@ -1,18 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Exynos - Memory map definitions
*/
#ifndef __ASM_ARCH_MAP_H
#define __ASM_ARCH_MAP_H __FILE__
#include <plat/map-base.h>
#include <plat/map-s5p.h>
#define EXYNOS_PA_CHIPID 0x10000000
#endif /* __ASM_ARCH_MAP_H */

4
arch/arm/mach-exynos/platsmp.c
View File

@ -22,8 +22,6 @@
#include <asm/smp_scu.h>
#include <asm/firmware.h>
#include <mach/map.h>
#include "common.h"
extern void exynos4_secondary_startup(void);
@ -188,7 +186,7 @@ void exynos_scu_enable(void)
static void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
if (soc_is_exynos4210() && exynos_rev() == EXYNOS4210_REV_1_1)
return pmu_base_addr + S5P_INFORM5;
return sysram_base_addr;
}

8
arch/arm/mach-exynos/pm.c
View File

@ -26,18 +26,18 @@
static inline void __iomem *exynos_boot_vector_addr(void)
{
if (samsung_rev() == EXYNOS4210_REV_1_1)
if (exynos_rev() == EXYNOS4210_REV_1_1)
return pmu_base_addr + S5P_INFORM7;
else if (samsung_rev() == EXYNOS4210_REV_1_0)
else if (exynos_rev() == EXYNOS4210_REV_1_0)
return sysram_base_addr + 0x24;
return pmu_base_addr + S5P_INFORM0;
}
static inline void __iomem *exynos_boot_vector_flag(void)
{
if (samsung_rev() == EXYNOS4210_REV_1_1)
if (exynos_rev() == EXYNOS4210_REV_1_1)
return pmu_base_addr + S5P_INFORM6;
else if (samsung_rev() == EXYNOS4210_REV_1_0)
else if (exynos_rev() == EXYNOS4210_REV_1_0)
return sysram_base_addr + 0x20;
return pmu_base_addr + S5P_INFORM1;
}

17
arch/arm/plat-samsung/cpu.c
View File

@ -14,13 +14,6 @@
#include <plat/cpu.h>
unsigned long samsung_cpu_id;
static unsigned int samsung_cpu_rev;
unsigned int samsung_rev(void)
{
return samsung_cpu_rev;
}
EXPORT_SYMBOL(samsung_rev);
void __init s3c64xx_init_cpu(void)
{
@ -34,15 +27,5 @@ void __init s3c64xx_init_cpu(void)
samsung_cpu_id = readl_relaxed(S3C_VA_SYS + 0xA1C);
}
samsung_cpu_rev = 0;
pr_info("Samsung CPU ID: 0x%08lx\n", samsung_cpu_id);
}
void __init s5p_init_cpu(const void __iomem *cpuid_addr)
{
samsung_cpu_id = readl_relaxed(cpuid_addr);
samsung_cpu_rev = samsung_cpu_id & 0xFF;
pr_info("Samsung CPU ID: 0x%08lx\n", samsung_cpu_id);
}

3
arch/arm/plat-samsung/include/plat/cpu.h
View File

@ -109,9 +109,6 @@ extern void s3c_init_cpu(unsigned long idcode,
extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
extern void s3c64xx_init_cpu(void);
extern void s5p_init_cpu(const void __iomem *cpuid_addr);
extern unsigned int samsung_rev(void);
extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);

2
arch/arm/plat-samsung/include/plat/map-s5p.h
View File

@ -9,8 +9,6 @@
#ifndef __ASM_PLAT_MAP_S5P_H
#define __ASM_PLAT_MAP_S5P_H __FILE__
#define S5P_VA_CHIPID S3C_ADDR(0x02000000)
#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
#define VA_VIC0 VA_VIC(0)
#define VA_VIC1 VA_VIC(1)