mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-14 12:37:32 +00:00
Merge branch 'for-3.9/scu-base-rework' into for-3.9/soc-t114
Conflicts: arch/arm/mach-tegra/platsmp.c
This commit is contained in:
commit
ee05948517
12 changed files with 141 additions and 68 deletions
|
@ -489,6 +489,23 @@ sdhci@c8000600 {
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||||||
status = "disabled";
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status = "disabled";
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||||||
};
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};
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|
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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};
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};
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pmu {
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pmu {
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compatible = "arm,cortex-a9-pmu";
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 56 0x04
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interrupts = <0 56 0x04
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@ -506,6 +506,35 @@ sdhci@78000600 {
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status = "disabled";
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status = "disabled";
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <3>;
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};
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};
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pmu {
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pmu {
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compatible = "arm,cortex-a9-pmu";
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 144 0x04
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interrupts = <0 144 0x04
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|
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@ -64,6 +64,24 @@ extern unsigned int processor_id;
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#define read_cpuid_ext(reg) 0
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#define read_cpuid_ext(reg) 0
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#endif
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#endif
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#define ARM_CPU_IMP_ARM 0x41
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#define ARM_CPU_IMP_INTEL 0x69
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#define ARM_CPU_PART_ARM1136 0xB360
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#define ARM_CPU_PART_ARM1156 0xB560
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#define ARM_CPU_PART_ARM1176 0xB760
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#define ARM_CPU_PART_ARM11MPCORE 0xB020
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#define ARM_CPU_PART_CORTEX_A8 0xC080
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#define ARM_CPU_PART_CORTEX_A9 0xC090
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#define ARM_CPU_PART_CORTEX_A5 0xC050
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#define ARM_CPU_PART_CORTEX_A15 0xC0F0
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#define ARM_CPU_PART_CORTEX_A7 0xC070
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#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
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#define ARM_CPU_XSCALE_ARCH_V1 0x2000
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#define ARM_CPU_XSCALE_ARCH_V2 0x4000
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#define ARM_CPU_XSCALE_ARCH_V3 0x6000
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/*
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/*
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* The CPU ID never changes at run time, so we might as well tell the
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* The CPU ID never changes at run time, so we might as well tell the
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* compiler that it's constant. Use this function to read the CPU ID
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* compiler that it's constant. Use this function to read the CPU ID
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@ -74,6 +92,21 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
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return read_cpuid(CPUID_ID);
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return read_cpuid(CPUID_ID);
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}
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}
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static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
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{
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return (read_cpuid_id() & 0xFF000000) >> 24;
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}
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static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
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{
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return read_cpuid_id() & 0xFFF0;
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}
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static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
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{
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return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK;
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}
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static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
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static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
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{
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{
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return read_cpuid(CPUID_CACHETYPE);
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return read_cpuid(CPUID_CACHETYPE);
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|
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@ -6,6 +6,23 @@
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#define SCU_PM_POWEROFF 3
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#define SCU_PM_POWEROFF 3
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#ifndef __ASSEMBLER__
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#ifndef __ASSEMBLER__
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#include <asm/cputype.h>
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static inline bool scu_a9_has_base(void)
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{
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return read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9;
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}
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static inline unsigned long scu_a9_get_base(void)
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{
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unsigned long pa;
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (pa));
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return pa;
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}
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unsigned int scu_get_core_count(void __iomem *);
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unsigned int scu_get_core_count(void __iomem *);
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void scu_enable(void __iomem *);
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void scu_enable(void __iomem *);
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int scu_power_mode(void __iomem *, unsigned int);
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int scu_power_mode(void __iomem *, unsigned int);
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@ -149,12 +149,6 @@ u64 armpmu_event_update(struct perf_event *event)
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static void
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static void
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armpmu_read(struct perf_event *event)
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armpmu_read(struct perf_event *event)
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{
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{
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struct hw_perf_event *hwc = &event->hw;
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/* Don't read disabled counters! */
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if (hwc->idx < 0)
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return;
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armpmu_event_update(event);
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armpmu_event_update(event);
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}
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}
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@ -207,8 +201,6 @@ armpmu_del(struct perf_event *event, int flags)
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struct hw_perf_event *hwc = &event->hw;
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struct hw_perf_event *hwc = &event->hw;
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int idx = hwc->idx;
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int idx = hwc->idx;
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WARN_ON(idx < 0);
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armpmu_stop(event, PERF_EF_UPDATE);
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armpmu_stop(event, PERF_EF_UPDATE);
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hw_events->events[idx] = NULL;
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hw_events->events[idx] = NULL;
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clear_bit(idx, hw_events->used_mask);
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clear_bit(idx, hw_events->used_mask);
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@ -358,7 +350,7 @@ __hw_perf_event_init(struct perf_event *event)
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{
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{
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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struct hw_perf_event *hwc = &event->hw;
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struct hw_perf_event *hwc = &event->hw;
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int mapping, err;
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int mapping;
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mapping = armpmu->map_event(event);
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mapping = armpmu->map_event(event);
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@ -407,14 +399,12 @@ __hw_perf_event_init(struct perf_event *event)
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local64_set(&hwc->period_left, hwc->sample_period);
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local64_set(&hwc->period_left, hwc->sample_period);
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}
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}
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err = 0;
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if (event->group_leader != event) {
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if (event->group_leader != event) {
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err = validate_group(event);
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if (validate_group(event) != 0);
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if (err)
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return -EINVAL;
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return -EINVAL;
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}
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}
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return err;
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return 0;
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}
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}
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static int armpmu_event_init(struct perf_event *event)
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static int armpmu_event_init(struct perf_event *event)
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@ -147,7 +147,7 @@ static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
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cpu_pmu->free_irq = cpu_pmu_free_irq;
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cpu_pmu->free_irq = cpu_pmu_free_irq;
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/* Ensure the PMU has sane values out of reset. */
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/* Ensure the PMU has sane values out of reset. */
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if (cpu_pmu && cpu_pmu->reset)
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if (cpu_pmu->reset)
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on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
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on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
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}
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}
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@ -201,48 +201,46 @@ static struct platform_device_id cpu_pmu_plat_device_ids[] = {
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static int probe_current_pmu(struct arm_pmu *pmu)
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static int probe_current_pmu(struct arm_pmu *pmu)
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{
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{
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int cpu = get_cpu();
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int cpu = get_cpu();
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unsigned long cpuid = read_cpuid_id();
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unsigned long implementor = read_cpuid_implementor();
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unsigned long implementor = (cpuid & 0xFF000000) >> 24;
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unsigned long part_number = read_cpuid_part_number();
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unsigned long part_number = (cpuid & 0xFFF0);
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int ret = -ENODEV;
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int ret = -ENODEV;
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||||||
|
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pr_info("probing PMU on CPU %d\n", cpu);
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pr_info("probing PMU on CPU %d\n", cpu);
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|
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||||||
/* ARM Ltd CPUs. */
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/* ARM Ltd CPUs. */
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if (0x41 == implementor) {
|
if (implementor == ARM_CPU_IMP_ARM) {
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switch (part_number) {
|
switch (part_number) {
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case 0xB360: /* ARM1136 */
|
case ARM_CPU_PART_ARM1136:
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case 0xB560: /* ARM1156 */
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case ARM_CPU_PART_ARM1156:
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case 0xB760: /* ARM1176 */
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case ARM_CPU_PART_ARM1176:
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ret = armv6pmu_init(pmu);
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ret = armv6pmu_init(pmu);
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break;
|
break;
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||||||
case 0xB020: /* ARM11mpcore */
|
case ARM_CPU_PART_ARM11MPCORE:
|
||||||
ret = armv6mpcore_pmu_init(pmu);
|
ret = armv6mpcore_pmu_init(pmu);
|
||||||
break;
|
break;
|
||||||
case 0xC080: /* Cortex-A8 */
|
case ARM_CPU_PART_CORTEX_A8:
|
||||||
ret = armv7_a8_pmu_init(pmu);
|
ret = armv7_a8_pmu_init(pmu);
|
||||||
break;
|
break;
|
||||||
case 0xC090: /* Cortex-A9 */
|
case ARM_CPU_PART_CORTEX_A9:
|
||||||
ret = armv7_a9_pmu_init(pmu);
|
ret = armv7_a9_pmu_init(pmu);
|
||||||
break;
|
break;
|
||||||
case 0xC050: /* Cortex-A5 */
|
case ARM_CPU_PART_CORTEX_A5:
|
||||||
ret = armv7_a5_pmu_init(pmu);
|
ret = armv7_a5_pmu_init(pmu);
|
||||||
break;
|
break;
|
||||||
case 0xC0F0: /* Cortex-A15 */
|
case ARM_CPU_PART_CORTEX_A15:
|
||||||
ret = armv7_a15_pmu_init(pmu);
|
ret = armv7_a15_pmu_init(pmu);
|
||||||
break;
|
break;
|
||||||
case 0xC070: /* Cortex-A7 */
|
case ARM_CPU_PART_CORTEX_A7:
|
||||||
ret = armv7_a7_pmu_init(pmu);
|
ret = armv7_a7_pmu_init(pmu);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
/* Intel CPUs [xscale]. */
|
/* Intel CPUs [xscale]. */
|
||||||
} else if (0x69 == implementor) {
|
} else if (implementor == ARM_CPU_IMP_INTEL) {
|
||||||
part_number = (cpuid >> 13) & 0x7;
|
switch (xscale_cpu_arch_version()) {
|
||||||
switch (part_number) {
|
case ARM_CPU_XSCALE_ARCH_V1:
|
||||||
case 1:
|
|
||||||
ret = xscale1pmu_init(pmu);
|
ret = xscale1pmu_init(pmu);
|
||||||
break;
|
break;
|
||||||
case 2:
|
case ARM_CPU_XSCALE_ARCH_V2:
|
||||||
ret = xscale2pmu_init(pmu);
|
ret = xscale2pmu_init(pmu);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
|
@ -279,17 +277,22 @@ static int cpu_pmu_device_probe(struct platform_device *pdev)
|
||||||
}
|
}
|
||||||
|
|
||||||
if (ret) {
|
if (ret) {
|
||||||
pr_info("failed to register PMU devices!");
|
pr_info("failed to probe PMU!");
|
||||||
kfree(pmu);
|
goto out_free;
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
cpu_pmu = pmu;
|
cpu_pmu = pmu;
|
||||||
cpu_pmu->plat_device = pdev;
|
cpu_pmu->plat_device = pdev;
|
||||||
cpu_pmu_init(cpu_pmu);
|
cpu_pmu_init(cpu_pmu);
|
||||||
armpmu_register(cpu_pmu, PERF_TYPE_RAW);
|
ret = armpmu_register(cpu_pmu, PERF_TYPE_RAW);
|
||||||
|
|
||||||
return 0;
|
if (!ret)
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
out_free:
|
||||||
|
pr_info("failed to register PMU devices!");
|
||||||
|
kfree(pmu);
|
||||||
|
return ret;
|
||||||
}
|
}
|
||||||
|
|
||||||
static struct platform_driver cpu_pmu_driver = {
|
static struct platform_driver cpu_pmu_driver = {
|
||||||
|
|
|
@ -106,7 +106,7 @@ static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
||||||
},
|
},
|
||||||
[C(OP_WRITE)] = {
|
[C(OP_WRITE)] = {
|
||||||
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||||
[C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
||||||
},
|
},
|
||||||
[C(OP_PREFETCH)] = {
|
[C(OP_PREFETCH)] = {
|
||||||
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||||
|
@ -259,7 +259,7 @@ static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
||||||
},
|
},
|
||||||
[C(OP_WRITE)] = {
|
[C(OP_WRITE)] = {
|
||||||
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||||
[C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
||||||
},
|
},
|
||||||
[C(OP_PREFETCH)] = {
|
[C(OP_PREFETCH)] = {
|
||||||
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||||
|
|
|
@ -157,8 +157,8 @@ static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
||||||
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
||||||
},
|
},
|
||||||
[C(OP_WRITE)] = {
|
[C(OP_WRITE)] = {
|
||||||
[C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS,
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||||
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
||||||
},
|
},
|
||||||
[C(OP_PREFETCH)] = {
|
[C(OP_PREFETCH)] = {
|
||||||
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||||
|
@ -282,7 +282,7 @@ static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
||||||
},
|
},
|
||||||
[C(OP_WRITE)] = {
|
[C(OP_WRITE)] = {
|
||||||
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||||
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
||||||
},
|
},
|
||||||
[C(OP_PREFETCH)] = {
|
[C(OP_PREFETCH)] = {
|
||||||
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||||
|
@ -399,8 +399,8 @@ static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
||||||
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
||||||
},
|
},
|
||||||
[C(OP_WRITE)] = {
|
[C(OP_WRITE)] = {
|
||||||
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||||
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
||||||
},
|
},
|
||||||
/*
|
/*
|
||||||
* The prefetch counters don't differentiate between the I
|
* The prefetch counters don't differentiate between the I
|
||||||
|
@ -527,8 +527,8 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
||||||
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
||||||
},
|
},
|
||||||
[C(OP_WRITE)] = {
|
[C(OP_WRITE)] = {
|
||||||
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||||
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
||||||
},
|
},
|
||||||
[C(OP_PREFETCH)] = {
|
[C(OP_PREFETCH)] = {
|
||||||
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||||
|
@ -651,8 +651,8 @@ static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
||||||
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
||||||
},
|
},
|
||||||
[C(OP_WRITE)] = {
|
[C(OP_WRITE)] = {
|
||||||
[C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS,
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||||
[C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL,
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
||||||
},
|
},
|
||||||
[C(OP_PREFETCH)] = {
|
[C(OP_PREFETCH)] = {
|
||||||
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||||
|
|
|
@ -83,7 +83,7 @@ static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
|
||||||
},
|
},
|
||||||
[C(OP_WRITE)] = {
|
[C(OP_WRITE)] = {
|
||||||
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||||
[C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS,
|
[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
|
||||||
},
|
},
|
||||||
[C(OP_PREFETCH)] = {
|
[C(OP_PREFETCH)] = {
|
||||||
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
|
||||||
|
|
|
@ -215,7 +215,7 @@ static void __init omap4_smp_init_cpus(void)
|
||||||
* Currently we can't call ioremap here because
|
* Currently we can't call ioremap here because
|
||||||
* SoC detection won't work until after init_early.
|
* SoC detection won't work until after init_early.
|
||||||
*/
|
*/
|
||||||
scu_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_SCU_BASE);
|
scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
|
||||||
BUG_ON(!scu_base);
|
BUG_ON(!scu_base);
|
||||||
ncores = scu_get_core_count(scu_base);
|
ncores = scu_get_core_count(scu_base);
|
||||||
} else if (cpu_id == CPU_CORTEX_A15) {
|
} else if (cpu_id == CPU_CORTEX_A15) {
|
||||||
|
|
|
@ -40,7 +40,6 @@
|
||||||
#define OMAP44XX_GIC_DIST_BASE 0x48241000
|
#define OMAP44XX_GIC_DIST_BASE 0x48241000
|
||||||
#define OMAP44XX_GIC_CPU_BASE 0x48240100
|
#define OMAP44XX_GIC_CPU_BASE 0x48240100
|
||||||
#define OMAP44XX_IRQ_GIC_START 32
|
#define OMAP44XX_IRQ_GIC_START 32
|
||||||
#define OMAP44XX_SCU_BASE 0x48240000
|
|
||||||
#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
|
#define OMAP44XX_LOCAL_TWD_BASE 0x48240600
|
||||||
#define OMAP44XX_L2CACHE_BASE 0x48242000
|
#define OMAP44XX_L2CACHE_BASE 0x48242000
|
||||||
#define OMAP44XX_WKUPGEN_BASE 0x48281000
|
#define OMAP44XX_WKUPGEN_BASE 0x48281000
|
||||||
|
|
|
@ -38,7 +38,6 @@
|
||||||
extern void tegra_secondary_startup(void);
|
extern void tegra_secondary_startup(void);
|
||||||
|
|
||||||
static cpumask_t tegra_cpu_init_mask;
|
static cpumask_t tegra_cpu_init_mask;
|
||||||
static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
|
|
||||||
|
|
||||||
#define EVP_CPU_RESET_VECTOR \
|
#define EVP_CPU_RESET_VECTOR \
|
||||||
(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
|
(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
|
||||||
|
@ -177,23 +176,8 @@ static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct *
|
||||||
return status;
|
return status;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
|
||||||
* Initialise the CPU possible map early - this describes the CPUs
|
|
||||||
* which may be present or become present in the system.
|
|
||||||
*/
|
|
||||||
static void __init tegra_smp_init_cpus(void)
|
static void __init tegra_smp_init_cpus(void)
|
||||||
{
|
{
|
||||||
unsigned int i, ncores = scu_get_core_count(scu_base);
|
|
||||||
|
|
||||||
if (ncores > nr_cpu_ids) {
|
|
||||||
pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
|
|
||||||
ncores, nr_cpu_ids);
|
|
||||||
ncores = nr_cpu_ids;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (i = 0; i < ncores; i++)
|
|
||||||
set_cpu_possible(i, true);
|
|
||||||
|
|
||||||
set_smp_cross_call(gic_raise_softirq);
|
set_smp_cross_call(gic_raise_softirq);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -202,7 +186,8 @@ static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
|
||||||
/* Always mark the boot CPU (CPU0) as initialized. */
|
/* Always mark the boot CPU (CPU0) as initialized. */
|
||||||
cpumask_set_cpu(0, &tegra_cpu_init_mask);
|
cpumask_set_cpu(0, &tegra_cpu_init_mask);
|
||||||
|
|
||||||
scu_enable(scu_base);
|
if (scu_a9_has_base())
|
||||||
|
scu_enable(IO_ADDRESS(scu_a9_get_base()));
|
||||||
}
|
}
|
||||||
|
|
||||||
struct smp_operations tegra_smp_ops __initdata = {
|
struct smp_operations tegra_smp_ops __initdata = {
|
||||||
|
|
Loading…
Reference in a new issue