mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-09-30 14:19:16 +00:00
Code Issues Releases Wiki Activity

dt-bindings: net: dwmac-meson: Document the "timing-adjustment" clock

Browse source 
The PRG_ETHERNET registers can add an RX delay in RGMII mode. This
requires an internal re-timing circuit whose input clock is called
"timing adjustment clock". Document this clock input so the clock can be
enabled as needed.

Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Martin Blumenstingl 2020-05-12 23:10:57 +02:00 committed by David S. Miller
parent 7af4c8451d
commit ee0b8e6d02
1 changed files with 7 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
View file

@ -40,18 +40,22 @@ allOf:
then:
properties:
clocks:
minItems: 3
maxItems: 4
items:
- description: GMAC main clock
- description: First parent clock of the internal mux
- description: Second parent clock of the internal mux
- description: The clock which drives the timing adjustment logic
clock-names:
minItems: 3
maxItems: 3
maxItems: 4
items:
- const: stmmaceth
- const: clkin0
- const: clkin1
- const: timing-adjustment
amlogic,tx-delay-ns:
$ref: /schemas/types.yaml#definitions/uint32
@ -120,7 +124,7 @@ examples:
reg = <0xc9410000 0x10000>, <0xc8834540 0x8>;
interrupts = <8>;
interrupt-names = "macirq";
clocks = <&clk_eth>, <&clkc_fclk_div2>, <&clk_mpll2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
clocks = <&clk_eth>, <&clk_fclk_div2>, <&clk_mpll2>, <&clk_fclk_div2>;
clock-names = "stmmaceth", "clkin0", "clkin1", "timing-adjustment";
phy-mode = "rgmii";
};