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perf vendors events arm64: Arm Cortex-A34
Add PMU events for Arm Cortex-A34 Add corresponding common events Update mapfile.csv Event data based on: https://github.com/ARM-software/data/tree/master/pmu/cortex-a34.json which is based on PMU event descriptions from the Arm Cortex-A34 Technical Reference Manual. Common event data based on: https://github.com/ARM-software/data/blob/master/pmu/common_armv9.json which is based on PMU event descriptions found in the Arm Architecture Reference Manual: https://developer.arm.com/documentation/ddi0487/ Mapping data (for mapfile.csv) based on: https://github.com/ARM-software/data/blob/master/cpus.json which is based on Main ID Register (MIDR) information found in the Arm Technical Reference Manuals for individual CPUs. Reviewed-by: John Garry <john.garry@huawei.com> Signed-off-by: Nick Forrington <nick.forrington@arm.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Andrew Kilroy <andrew.kilroy@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mike Leach <mike.leach@linaro.org> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Will Deacon <will@kernel.org> Cc: linux-arm-kernel@lists.infradead.org Link: https://lore.kernel.org/r/20220520181455.340344-2-nick.forrington@arm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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11
tools/perf/pmu-events/arch/arm64/arm/cortex-a34/branch.json
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11
tools/perf/pmu-events/arch/arm64/arm/cortex-a34/branch.json
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@ -0,0 +1,11 @@
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[
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{
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"ArchStdEvent": "BR_MIS_PRED"
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},
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{
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"ArchStdEvent": "BR_PRED"
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},
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{
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"ArchStdEvent": "BR_INDIRECT_SPEC"
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}
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]
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17
tools/perf/pmu-events/arch/arm64/arm/cortex-a34/bus.json
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tools/perf/pmu-events/arch/arm64/arm/cortex-a34/bus.json
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[
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{
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"ArchStdEvent": "CPU_CYCLES"
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},
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{
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"ArchStdEvent": "BUS_ACCESS"
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},
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{
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"ArchStdEvent": "BUS_CYCLES"
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},
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{
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"ArchStdEvent": "BUS_ACCESS_RD"
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},
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{
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"ArchStdEvent": "BUS_ACCESS_WR"
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}
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]
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32
tools/perf/pmu-events/arch/arm64/arm/cortex-a34/cache.json
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tools/perf/pmu-events/arch/arm64/arm/cortex-a34/cache.json
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[
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{
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"ArchStdEvent": "L1I_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L1I_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L1D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L1D_CACHE"
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},
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{
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"ArchStdEvent": "L1D_TLB_REFILL"
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},
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{
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"ArchStdEvent": "L1I_CACHE"
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},
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{
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"ArchStdEvent": "L1D_CACHE_WB"
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},
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{
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"ArchStdEvent": "L2D_CACHE"
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},
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{
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"ArchStdEvent": "L2D_CACHE_REFILL"
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},
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{
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"ArchStdEvent": "L2D_CACHE_WB"
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}
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]
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@ -0,0 +1,14 @@
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[
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{
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"ArchStdEvent": "EXC_TAKEN"
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},
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{
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"ArchStdEvent": "MEMORY_ERROR"
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},
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{
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"ArchStdEvent": "EXC_IRQ"
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},
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{
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"ArchStdEvent": "EXC_FIQ"
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}
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]
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[
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{
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"ArchStdEvent": "SW_INCR"
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},
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{
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"ArchStdEvent": "LD_RETIRED"
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},
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{
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"ArchStdEvent": "ST_RETIRED"
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},
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{
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"ArchStdEvent": "INST_RETIRED"
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},
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{
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"ArchStdEvent": "EXC_RETURN"
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},
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{
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"ArchStdEvent": "CID_WRITE_RETIRED"
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},
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{
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"ArchStdEvent": "PC_WRITE_RETIRED"
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},
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{
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"ArchStdEvent": "BR_IMMED_RETIRED"
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},
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{
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"ArchStdEvent": "BR_RETURN_RETIRED"
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}
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]
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@ -0,0 +1,8 @@
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[
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{
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"ArchStdEvent": "UNALIGNED_LDST_RETIRED"
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},
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{
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"ArchStdEvent": "MEM_ACCESS"
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}
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]
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@ -35,6 +35,18 @@
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"EventName": "L1D_TLB_REFILL",
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"BriefDescription": "Attributable Level 1 data TLB refill"
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},
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{
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"PublicDescription": "Instruction architecturally executed, condition code check pass, load",
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"EventCode": "0x06",
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"EventName": "LD_RETIRED",
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"BriefDescription": "Instruction architecturally executed, condition code check pass, load"
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},
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{
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"PublicDescription": "Instruction architecturally executed, condition code check pass, store",
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"EventCode": "0x07",
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"EventName": "ST_RETIRED",
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"BriefDescription": "Instruction architecturally executed, condition code check pass, store"
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},
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{
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"PublicDescription": "Instruction architecturally executed",
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"EventCode": "0x08",
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@ -59,6 +71,30 @@
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"EventName": "CID_WRITE_RETIRED",
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"BriefDescription": "Instruction architecturally executed, condition code check pass, write to CONTEXTIDR"
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},
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{
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"PublicDescription": "Instruction architecturally executed, condition code check pass, software change of the PC",
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"EventCode": "0x0C",
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"EventName": "PC_WRITE_RETIRED",
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"BriefDescription": "Instruction architecturally executed, condition code check pass, software change of the PC"
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},
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{
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"PublicDescription": "Instruction architecturally executed, immediate branch",
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"EventCode": "0x0D",
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"EventName": "BR_IMMED_RETIRED",
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"BriefDescription": "Instruction architecturally executed, immediate branch"
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},
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{
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"PublicDescription": "Instruction architecturally executed, condition code check pass, procedure return",
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"EventCode": "0x0E",
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"EventName": "BR_RETURN_RETIRED",
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"BriefDescription": "Instruction architecturally executed, condition code check pass, procedure return"
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},
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{
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"PublicDescription": "Instruction architecturally executed, condition code check pass, unaligned",
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"EventCode": "0x0F",
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"EventName": "UNALIGNED_LDST_RETIRED",
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"BriefDescription": "Instruction architecturally executed, condition code check pass, unaligned"
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},
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{
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"PublicDescription": "Mispredicted or not predicted branch speculatively executed",
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"EventCode": "0x10",
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@ -12,6 +12,7 @@
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#
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#
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#Family-model,Version,Filename,EventType
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0x00000000410fd020,v1,arm/cortex-a34,core
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0x00000000410fd030,v1,arm/cortex-a53,core
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0x00000000420f1000,v1,arm/cortex-a53,core
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0x00000000410fd070,v1,arm/cortex-a57-a72,core
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