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iw_cxgb4: Max fastreg depth depends on DSGL support
The max depth of a fastreg mr depends on whether the device supports DSGL or not. So compute it dynamically based on the device support and the module use_dsgl option. Signed-off-by: Steve Wise <swise@opengridcomputing.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
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3 changed files with 12 additions and 11 deletions
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@ -617,12 +617,14 @@ struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd,
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int ret = 0;
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int ret = 0;
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int length = roundup(max_num_sg * sizeof(u64), 32);
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int length = roundup(max_num_sg * sizeof(u64), 32);
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if (mr_type != IB_MR_TYPE_MEM_REG ||
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max_num_sg > t4_max_fr_depth(use_dsgl))
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return ERR_PTR(-EINVAL);
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php = to_c4iw_pd(pd);
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php = to_c4iw_pd(pd);
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rhp = php->rhp;
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rhp = php->rhp;
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if (mr_type != IB_MR_TYPE_MEM_REG ||
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max_num_sg > t4_max_fr_depth(&rhp->rdev.lldi.ulptx_memwrite_dsgl &&
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use_dsgl))
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return ERR_PTR(-EINVAL);
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mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
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mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
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if (!mhp) {
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if (!mhp) {
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ret = -ENOMEM;
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ret = -ENOMEM;
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@ -339,7 +339,8 @@ static int c4iw_query_device(struct ib_device *ibdev, struct ib_device_attr *pro
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props->max_mr = c4iw_num_stags(&dev->rdev);
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props->max_mr = c4iw_num_stags(&dev->rdev);
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props->max_pd = T4_MAX_NUM_PD;
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props->max_pd = T4_MAX_NUM_PD;
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props->local_ca_ack_delay = 0;
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props->local_ca_ack_delay = 0;
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props->max_fast_reg_page_list_len = t4_max_fr_depth(use_dsgl);
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props->max_fast_reg_page_list_len =
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t4_max_fr_depth(dev->rdev.lldi.ulptx_memwrite_dsgl && use_dsgl);
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return 0;
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return 0;
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}
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}
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@ -606,7 +606,7 @@ static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
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}
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}
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static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
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static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
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struct ib_reg_wr *wr, u8 *len16, u8 t5dev)
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struct ib_reg_wr *wr, u8 *len16, bool dsgl_supported)
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{
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{
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struct c4iw_mr *mhp = to_c4iw_mr(wr->mr);
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struct c4iw_mr *mhp = to_c4iw_mr(wr->mr);
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struct fw_ri_immd *imdp;
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struct fw_ri_immd *imdp;
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@ -615,7 +615,7 @@ static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
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int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32);
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int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32);
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int rem;
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int rem;
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if (mhp->mpl_len > t4_max_fr_depth(use_dsgl))
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if (mhp->mpl_len > t4_max_fr_depth(dsgl_supported && use_dsgl))
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return -EINVAL;
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return -EINVAL;
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wqe->fr.qpbinde_to_dcacpu = 0;
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wqe->fr.qpbinde_to_dcacpu = 0;
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@ -629,7 +629,7 @@ static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
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wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova &
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wqe->fr.va_lo_fbo = cpu_to_be32(mhp->ibmr.iova &
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0xffffffff);
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0xffffffff);
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if (t5dev && use_dsgl && (pbllen > max_fr_immd)) {
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if (dsgl_supported && use_dsgl && (pbllen > max_fr_immd)) {
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struct fw_ri_dsgl *sglp;
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struct fw_ri_dsgl *sglp;
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for (i = 0; i < mhp->mpl_len; i++)
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for (i = 0; i < mhp->mpl_len; i++)
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@ -808,9 +808,7 @@ int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
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fw_opcode = FW_RI_FR_NSMR_WR;
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fw_opcode = FW_RI_FR_NSMR_WR;
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swsqe->opcode = FW_RI_FAST_REGISTER;
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swsqe->opcode = FW_RI_FAST_REGISTER;
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err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr), &len16,
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err = build_memreg(&qhp->wq.sq, wqe, reg_wr(wr), &len16,
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is_t5(
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qhp->rhp->rdev.lldi.ulptx_memwrite_dsgl);
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qhp->rhp->rdev.lldi.adapter_type) ?
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1 : 0);
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break;
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break;
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case IB_WR_LOCAL_INV:
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case IB_WR_LOCAL_INV:
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if (wr->send_flags & IB_SEND_FENCE)
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if (wr->send_flags & IB_SEND_FENCE)
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