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spi: bcm-qspi: Add mspi spcr3 32/64-bits xfer mode
Adding 32-bits and 64-bits per transfer modes using the SPCR3 register settings provided in MSPI controller ver >= 1.5 Signed-off-by: Kamal Dasu <kdasu@broadcom.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Link: https://lore.kernel.org/r/20211008203603.40915-2-kdasu.kdev@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Kamal Dasu
Mark Brown
parent
75b3cb97eb
commit
ee4d62c473
1 changed files with 151 additions and 21 deletions
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@ -83,6 +83,9 @@
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/* MSPI register offsets */
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#define MSPI_SPCR0_LSB 0x000
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#define MSPI_SPCR0_MSB 0x004
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#define MSPI_SPCR0_MSB_CPHA BIT(0)
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#define MSPI_SPCR0_MSB_CPOL BIT(1)
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#define MSPI_SPCR0_MSB_BITS_SHIFT 0x2
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#define MSPI_SPCR1_LSB 0x008
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#define MSPI_SPCR1_MSB 0x00c
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#define MSPI_NEWQP 0x010
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@ -102,6 +105,7 @@
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#define MSPI_NUM_CDRAM 16
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#define MSPI_CDRAM_CONT_BIT BIT(7)
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#define MSPI_CDRAM_BITSE_BIT BIT(6)
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#define MSPI_CDRAM_DT_BIT BIT(5)
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#define MSPI_CDRAM_PCS 0xf
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#define MSPI_SPCR2_SPE BIT(6)
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@ -114,6 +118,12 @@
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~(BIT(10) | BIT(11)))
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#define MSPI_SPCR3_SYSCLKSEL_108 (MSPI_SPCR3_SYSCLKSEL_MASK & \
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BIT(11))
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#define MSPI_SPCR3_TXRXDAM_MASK GENMASK(4, 2)
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#define MSPI_SPCR3_DAM_8BYTE 0
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#define MSPI_SPCR3_DAM_16BYTE (BIT(2) | BIT(4))
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#define MSPI_SPCR3_DAM_32BYTE (BIT(3) | BIT(5))
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#define MSPI_SPCR3_DATA_REG_SZ BIT(8)
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#define MSPI_SPCR3_CPHARX BIT(9)
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#define MSPI_MSPI_STATUS_SPIF BIT(0)
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@ -153,6 +163,14 @@
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#define TRANS_STATUS_BREAK_DESELECT (TRANS_STATUS_BREAK_EOM | \
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TRANS_STATUS_BREAK_CS_CHANGE)
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/*
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* Used for writing and reading data in the right order
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* to TXRAM and RXRAM when used as 32-bit registers respectively
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*/
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#define swap4bytes(__val) \
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((((__val) >> 24) & 0x000000FF) | (((__val) >> 8) & 0x0000FF00) | \
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(((__val) << 8) & 0x00FF0000) | (((__val) << 24) & 0xFF000000))
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struct bcm_qspi_parms {
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u32 speed_hz;
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u8 mode;
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@ -261,7 +279,7 @@ static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi)
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static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi)
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{
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if (bcm_qspi_has_fastbr(qspi))
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return 1;
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return (bcm_qspi_has_sysclk_108(qspi) ? 4 : 1);
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else
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return 8;
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}
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@ -570,23 +588,23 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
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{
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u32 spcr, spbr = 0;
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if (xp->speed_hz)
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spbr = qspi->base_clk / (2 * xp->speed_hz);
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spcr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX);
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bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
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if (!qspi->mspi_maj_rev)
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/* legacy controller */
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spcr = MSPI_MASTER_BIT;
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else
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spcr = 0;
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/* for 16 bit the data should be zero */
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if (xp->bits_per_word != 16)
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spcr |= xp->bits_per_word << 2;
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spcr |= xp->mode & 3;
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/*
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* Bits per transfer. BITS determines the number of data bits
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* transferred if the command control bit (BITSE of a
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* CDRAM Register) is equal to 1.
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* If CDRAM BITSE is equal to 0, 8 data bits are transferred
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* regardless
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*/
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if (xp->bits_per_word != 16 && xp->bits_per_word != 64)
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spcr |= xp->bits_per_word << MSPI_SPCR0_MSB_BITS_SHIFT;
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spcr |= xp->mode & (MSPI_SPCR0_MSB_CPHA | MSPI_SPCR0_MSB_CPOL);
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bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
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if (bcm_qspi_has_fastbr(qspi)) {
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@ -599,13 +617,37 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
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/* SYSCLK_108 */
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spcr |= MSPI_SPCR3_SYSCLKSEL_108;
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qspi->base_clk = MSPI_BASE_FREQ * 4;
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/* Change spbr as we changed sysclk */
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bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, 4);
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}
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if (xp->bits_per_word > 16) {
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/* data_reg_size 1 (64bit) */
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spcr |= MSPI_SPCR3_DATA_REG_SZ;
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/* TxRx RAM data access mode 2 for 32B and set fastdt */
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spcr |= MSPI_SPCR3_DAM_32BYTE | MSPI_SPCR3_FASTDT;
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/*
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* Set length of delay after transfer
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* DTL from 0(256) to 1
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*/
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bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 1);
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} else {
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/* data_reg_size[8] = 0 */
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spcr &= ~(MSPI_SPCR3_DATA_REG_SZ);
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/*
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* TxRx RAM access mode 8B
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* and disable fastdt
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*/
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spcr &= ~(MSPI_SPCR3_DAM_32BYTE);
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}
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bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);
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}
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if (xp->speed_hz)
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spbr = qspi->base_clk / (2 * xp->speed_hz);
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spbr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX);
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bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spbr);
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qspi->last_parms = *xp;
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}
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@ -626,7 +668,7 @@ static int bcm_qspi_setup(struct spi_device *spi)
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{
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struct bcm_qspi_parms *xp;
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if (spi->bits_per_word > 16)
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if (spi->bits_per_word > 64)
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return -EINVAL;
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xp = spi_get_ctldata(spi);
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@ -665,8 +707,12 @@ static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
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/* count the last transferred bytes */
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if (qt->trans->bits_per_word <= 8)
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qt->byte++;
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else
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else if (qt->trans->bits_per_word <= 16)
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qt->byte += 2;
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else if (qt->trans->bits_per_word <= 32)
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qt->byte += 4;
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else if (qt->trans->bits_per_word <= 64)
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qt->byte += 8;
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if (qt->byte >= qt->trans->len) {
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/* we're at the end of the spi_transfer */
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@ -709,6 +755,33 @@ static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot)
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((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
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}
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static inline u32 read_rxram_slot_u32(struct bcm_qspi *qspi, int slot)
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{
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u32 reg_offset = MSPI_RXRAM;
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u32 offset = reg_offset + (slot << 3);
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u32 val;
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val = bcm_qspi_read(qspi, MSPI, offset);
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val = swap4bytes(val);
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return val;
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}
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static inline u64 read_rxram_slot_u64(struct bcm_qspi *qspi, int slot)
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{
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u32 reg_offset = MSPI_RXRAM;
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u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
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u32 msb_offset = reg_offset + (slot << 3);
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u32 msb, lsb;
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msb = bcm_qspi_read(qspi, MSPI, msb_offset);
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msb = swap4bytes(msb);
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lsb = bcm_qspi_read(qspi, MSPI, lsb_offset);
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lsb = swap4bytes(lsb);
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return ((u64)msb << 32 | lsb);
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}
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static void read_from_hw(struct bcm_qspi *qspi, int slots)
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{
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struct qspi_trans tp;
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@ -732,7 +805,7 @@ static void read_from_hw(struct bcm_qspi *qspi, int slots)
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buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
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dev_dbg(&qspi->pdev->dev, "RD %02x\n",
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buf ? buf[tp.byte] : 0x0);
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} else {
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} else if (tp.trans->bits_per_word <= 16) {
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u16 *buf = tp.trans->rx_buf;
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if (buf)
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@ -740,6 +813,25 @@ static void read_from_hw(struct bcm_qspi *qspi, int slots)
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slot);
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dev_dbg(&qspi->pdev->dev, "RD %04x\n",
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buf ? buf[tp.byte / 2] : 0x0);
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} else if (tp.trans->bits_per_word <= 32) {
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u32 *buf = tp.trans->rx_buf;
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if (buf)
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buf[tp.byte / 4] = read_rxram_slot_u32(qspi,
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slot);
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dev_dbg(&qspi->pdev->dev, "RD %08x\n",
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buf ? buf[tp.byte / 4] : 0x0);
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} else if (tp.trans->bits_per_word <= 64) {
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u64 *buf = tp.trans->rx_buf;
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if (buf)
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buf[tp.byte / 8] = read_rxram_slot_u64(qspi,
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slot);
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dev_dbg(&qspi->pdev->dev, "RD %llx\n",
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buf ? buf[tp.byte / 8] : 0x0);
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}
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update_qspi_trans_byte_count(qspi, &tp,
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@ -769,6 +861,28 @@ static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot,
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bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
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}
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static inline void write_txram_slot_u32(struct bcm_qspi *qspi, int slot,
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u32 val)
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{
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u32 reg_offset = MSPI_TXRAM;
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u32 msb_offset = reg_offset + (slot << 3);
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bcm_qspi_write(qspi, MSPI, msb_offset, swap4bytes(val));
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}
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static inline void write_txram_slot_u64(struct bcm_qspi *qspi, int slot,
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u64 val)
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{
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u32 reg_offset = MSPI_TXRAM;
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u32 msb_offset = reg_offset + (slot << 3);
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u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
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u32 msb = upper_32_bits(val);
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u32 lsb = lower_32_bits(val);
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bcm_qspi_write(qspi, MSPI, msb_offset, swap4bytes(msb));
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bcm_qspi_write(qspi, MSPI, lsb_offset, swap4bytes(lsb));
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}
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static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot)
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{
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return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
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@ -792,20 +906,39 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
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/* Run until end of transfer or reached the max data */
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while (!tstatus && slot < MSPI_NUM_CDRAM) {
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mspi_cdram = MSPI_CDRAM_CONT_BIT;
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if (tp.trans->bits_per_word <= 8) {
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const u8 *buf = tp.trans->tx_buf;
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u8 val = buf ? buf[tp.byte] : 0x00;
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write_txram_slot_u8(qspi, slot, val);
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dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
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} else {
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} else if (tp.trans->bits_per_word <= 16) {
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const u16 *buf = tp.trans->tx_buf;
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u16 val = buf ? buf[tp.byte / 2] : 0x0000;
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write_txram_slot_u16(qspi, slot, val);
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dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
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} else if (tp.trans->bits_per_word <= 32) {
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const u32 *buf = tp.trans->tx_buf;
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u32 val = buf ? buf[tp.byte/4] : 0x0;
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write_txram_slot_u32(qspi, slot, val);
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dev_dbg(&qspi->pdev->dev, "WR %08x\n", val);
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} else if (tp.trans->bits_per_word <= 64) {
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const u64 *buf = tp.trans->tx_buf;
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u64 val = (buf ? buf[tp.byte/8] : 0x0);
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/* use the length of delay from SPCR1_LSB */
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if (bcm_qspi_has_fastbr(qspi))
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mspi_cdram |= MSPI_CDRAM_DT_BIT;
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write_txram_slot_u64(qspi, slot, val);
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dev_dbg(&qspi->pdev->dev, "WR %llx\n", val);
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}
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mspi_cdram = MSPI_CDRAM_CONT_BIT;
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mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
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MSPI_CDRAM_BITSE_BIT);
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if (has_bspi(qspi))
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mspi_cdram &= ~1;
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@ -813,9 +946,6 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
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mspi_cdram |= (~(1 << spi->chip_select) &
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MSPI_CDRAM_PCS);
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mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
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MSPI_CDRAM_BITSE_BIT);
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write_cdram_slot(qspi, slot, mspi_cdram);
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tstatus = update_qspi_trans_byte_count(qspi, &tp,
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