rtw89: 8852c: adjust mactxen delay of mac/phy interface

mac_txen time is to inform TMAC tx after rx air end.
Modify 8852c value to meet TB SIFS time.

Signed-off-by: Chia-Yuan Li <leo.li@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220704023453.19935-7-pkshih@realtek.com
This commit is contained in:
Chia-Yuan Li 2022-07-04 10:34:53 +08:00 committed by Kalle Valo
parent 60b2ede9dd
commit ee54690464
2 changed files with 7 additions and 1 deletions

View file

@ -1754,7 +1754,12 @@ static int scheduler_init(struct rtw89_dev *rtwdev, u8 mac_idx)
return ret;
reg = rtw89_mac_reg_by_idx(R_AX_PREBKF_CFG_1, mac_idx);
rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, SIFS_MACTXEN_T1);
if (rtwdev->chip->chip_id == RTL8852C)
rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
SIFS_MACTXEN_T1_V1);
else
rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK,
SIFS_MACTXEN_T1);
if (rtwdev->chip->chip_id == RTL8852B) {
reg = rtw89_mac_reg_by_idx(R_AX_SCH_EXT_CTRL, mac_idx);

View file

@ -1877,6 +1877,7 @@
#define B_AX_SIFS_TIMEOUT_T2_MASK GENMASK(14, 8)
#define B_AX_SIFS_MACTXEN_T1_MASK GENMASK(6, 0)
#define SIFS_MACTXEN_T1 0x47
#define SIFS_MACTXEN_T1_V1 0x41
#define R_AX_CCA_CFG_0 0xC340
#define R_AX_CCA_CFG_0_C1 0xE340