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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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iavf: diet and reformat
Remove a bunch of unused code and reformat a few lines. Also remove some now un-necessary files. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Tested-by: Andrew Bowers <andrewx.bowers@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
Jesse Brandeburg
Jeff Kirsher
parent
8062b2263a
commit
ee61022acf
8 changed files with 6 additions and 4014 deletions
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@ -7,16 +7,6 @@
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#include "i40e_adminq.h"
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#include "i40e_prototype.h"
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/**
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* i40e_is_nvm_update_op - return true if this is an NVM update operation
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* @desc: API request descriptor
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**/
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static inline bool i40e_is_nvm_update_op(struct i40e_aq_desc *desc)
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{
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return (desc->opcode == i40e_aqc_opc_nvm_erase) ||
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(desc->opcode == i40e_aqc_opc_nvm_update);
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}
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/**
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* i40e_adminq_init_regs - Initialize AdminQ registers
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* @hw: pointer to the hardware structure
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@ -569,9 +559,6 @@ i40e_status i40evf_shutdown_adminq(struct i40e_hw *hw)
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i40e_shutdown_asq(hw);
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i40e_shutdown_arq(hw);
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if (hw->nvm_buff.va)
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i40e_free_virt_mem(hw, &hw->nvm_buff);
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return ret_code;
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}
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@ -951,17 +938,3 @@ i40e_status i40evf_clean_arq_element(struct i40e_hw *hw,
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return ret_code;
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}
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void i40evf_resume_aq(struct i40e_hw *hw)
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{
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/* Registers are reset after PF reset */
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hw->aq.asq.next_to_use = 0;
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hw->aq.asq.next_to_clean = 0;
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i40e_config_asq_regs(hw);
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hw->aq.arq.next_to_use = 0;
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hw->aq.arq.next_to_clean = 0;
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i40e_config_arq_regs(hw);
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}
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File diff suppressed because it is too large
Load diff
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@ -525,7 +525,6 @@ i40e_status i40evf_aq_set_rss_key(struct i40e_hw *hw,
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return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
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}
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/* The i40evf_ptype_lookup table is used to convert from the 8-bit ptype in the
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* hardware to a bit-field that can be used by SW to more easily determine the
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* packet type.
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@ -891,135 +890,6 @@ struct i40e_rx_ptype_decoded i40evf_ptype_lookup[] = {
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I40E_PTT_UNUSED_ENTRY(255)
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};
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/**
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* i40evf_aq_rx_ctl_read_register - use FW to read from an Rx control register
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* @hw: pointer to the hw struct
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* @reg_addr: register address
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* @reg_val: ptr to register value
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* @cmd_details: pointer to command details structure or NULL
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*
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* Use the firmware to read the Rx control register,
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* especially useful if the Rx unit is under heavy pressure
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**/
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i40e_status i40evf_aq_rx_ctl_read_register(struct i40e_hw *hw,
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u32 reg_addr, u32 *reg_val,
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struct i40e_asq_cmd_details *cmd_details)
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{
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struct i40e_aq_desc desc;
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struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
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(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
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i40e_status status;
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if (!reg_val)
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return I40E_ERR_PARAM;
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i40evf_fill_default_direct_cmd_desc(&desc,
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i40e_aqc_opc_rx_ctl_reg_read);
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cmd_resp->address = cpu_to_le32(reg_addr);
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status = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
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if (status == 0)
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*reg_val = le32_to_cpu(cmd_resp->value);
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return status;
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}
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/**
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* i40evf_read_rx_ctl - read from an Rx control register
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* @hw: pointer to the hw struct
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* @reg_addr: register address
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**/
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u32 i40evf_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
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{
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i40e_status status = 0;
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bool use_register;
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int retry = 5;
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u32 val = 0;
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use_register = (((hw->aq.api_maj_ver == 1) &&
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(hw->aq.api_min_ver < 5)) ||
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(hw->mac.type == I40E_MAC_X722));
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if (!use_register) {
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do_retry:
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status = i40evf_aq_rx_ctl_read_register(hw, reg_addr,
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&val, NULL);
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if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
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usleep_range(1000, 2000);
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retry--;
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goto do_retry;
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}
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}
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/* if the AQ access failed, try the old-fashioned way */
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if (status || use_register)
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val = rd32(hw, reg_addr);
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return val;
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}
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/**
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* i40evf_aq_rx_ctl_write_register
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* @hw: pointer to the hw struct
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* @reg_addr: register address
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* @reg_val: register value
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* @cmd_details: pointer to command details structure or NULL
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*
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* Use the firmware to write to an Rx control register,
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* especially useful if the Rx unit is under heavy pressure
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**/
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i40e_status i40evf_aq_rx_ctl_write_register(struct i40e_hw *hw,
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u32 reg_addr, u32 reg_val,
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struct i40e_asq_cmd_details *cmd_details)
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{
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struct i40e_aq_desc desc;
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struct i40e_aqc_rx_ctl_reg_read_write *cmd =
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(struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
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i40e_status status;
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i40evf_fill_default_direct_cmd_desc(&desc,
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i40e_aqc_opc_rx_ctl_reg_write);
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cmd->address = cpu_to_le32(reg_addr);
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cmd->value = cpu_to_le32(reg_val);
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status = i40evf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
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return status;
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}
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/**
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* i40evf_write_rx_ctl - write to an Rx control register
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* @hw: pointer to the hw struct
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* @reg_addr: register address
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* @reg_val: register value
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**/
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void i40evf_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
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{
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i40e_status status = 0;
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bool use_register;
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int retry = 5;
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use_register = (((hw->aq.api_maj_ver == 1) &&
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(hw->aq.api_min_ver < 5)) ||
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(hw->mac.type == I40E_MAC_X722));
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if (!use_register) {
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do_retry:
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status = i40evf_aq_rx_ctl_write_register(hw, reg_addr,
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reg_val, NULL);
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if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
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usleep_range(1000, 2000);
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retry--;
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goto do_retry;
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}
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}
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/* if the AQ access failed, try the old-fashioned way */
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if (status || use_register)
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wr32(hw, reg_addr, reg_val);
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}
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/**
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* i40e_aq_send_msg_to_pf
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* @hw: pointer to the hardware structure
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@ -1110,211 +980,3 @@ i40e_status i40e_vf_reset(struct i40e_hw *hw)
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return i40e_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
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0, NULL, 0, NULL);
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}
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/**
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* i40evf_aq_write_ddp - Write dynamic device personalization (ddp)
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* @hw: pointer to the hw struct
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* @buff: command buffer (size in bytes = buff_size)
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* @buff_size: buffer size in bytes
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* @track_id: package tracking id
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* @error_offset: returns error offset
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* @error_info: returns error information
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* @cmd_details: pointer to command details structure or NULL
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**/
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enum
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i40e_status_code i40evf_aq_write_ddp(struct i40e_hw *hw, void *buff,
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u16 buff_size, u32 track_id,
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u32 *error_offset, u32 *error_info,
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struct i40e_asq_cmd_details *cmd_details)
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{
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struct i40e_aq_desc desc;
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struct i40e_aqc_write_personalization_profile *cmd =
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(struct i40e_aqc_write_personalization_profile *)
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&desc.params.raw;
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struct i40e_aqc_write_ddp_resp *resp;
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i40e_status status;
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i40evf_fill_default_direct_cmd_desc(&desc,
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i40e_aqc_opc_write_personalization_profile);
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desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
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if (buff_size > I40E_AQ_LARGE_BUF)
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desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
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desc.datalen = cpu_to_le16(buff_size);
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cmd->profile_track_id = cpu_to_le32(track_id);
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status = i40evf_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
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if (!status) {
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resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
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if (error_offset)
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*error_offset = le32_to_cpu(resp->error_offset);
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if (error_info)
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*error_info = le32_to_cpu(resp->error_info);
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}
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return status;
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}
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/**
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* i40evf_aq_get_ddp_list - Read dynamic device personalization (ddp)
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* @hw: pointer to the hw struct
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* @buff: command buffer (size in bytes = buff_size)
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* @buff_size: buffer size in bytes
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* @flags: AdminQ command flags
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* @cmd_details: pointer to command details structure or NULL
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**/
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enum
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i40e_status_code i40evf_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
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u16 buff_size, u8 flags,
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struct i40e_asq_cmd_details *cmd_details)
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{
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struct i40e_aq_desc desc;
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struct i40e_aqc_get_applied_profiles *cmd =
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(struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
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i40e_status status;
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i40evf_fill_default_direct_cmd_desc(&desc,
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i40e_aqc_opc_get_personalization_profile_list);
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desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
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if (buff_size > I40E_AQ_LARGE_BUF)
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desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
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desc.datalen = cpu_to_le16(buff_size);
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cmd->flags = flags;
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status = i40evf_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
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return status;
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}
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/**
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* i40evf_find_segment_in_package
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* @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_I40E)
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* @pkg_hdr: pointer to the package header to be searched
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*
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* This function searches a package file for a particular segment type. On
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* success it returns a pointer to the segment header, otherwise it will
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* return NULL.
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**/
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struct i40e_generic_seg_header *
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i40evf_find_segment_in_package(u32 segment_type,
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struct i40e_package_header *pkg_hdr)
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{
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struct i40e_generic_seg_header *segment;
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u32 i;
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/* Search all package segments for the requested segment type */
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for (i = 0; i < pkg_hdr->segment_count; i++) {
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segment =
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(struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
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pkg_hdr->segment_offset[i]);
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if (segment->type == segment_type)
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return segment;
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}
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return NULL;
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}
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/**
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* i40evf_write_profile
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* @hw: pointer to the hardware structure
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* @profile: pointer to the profile segment of the package to be downloaded
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* @track_id: package tracking id
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*
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* Handles the download of a complete package.
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*/
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enum i40e_status_code
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i40evf_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
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u32 track_id)
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{
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i40e_status status = 0;
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struct i40e_section_table *sec_tbl;
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struct i40e_profile_section_header *sec = NULL;
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u32 dev_cnt;
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u32 vendor_dev_id;
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u32 *nvm;
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u32 section_size = 0;
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u32 offset = 0, info = 0;
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u32 i;
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dev_cnt = profile->device_table_count;
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for (i = 0; i < dev_cnt; i++) {
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vendor_dev_id = profile->device_table[i].vendor_dev_id;
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if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL)
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if (hw->device_id == (vendor_dev_id & 0xFFFF))
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break;
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}
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if (i == dev_cnt) {
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i40e_debug(hw, I40E_DEBUG_PACKAGE, "Device doesn't support DDP");
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return I40E_ERR_DEVICE_NOT_SUPPORTED;
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}
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nvm = (u32 *)&profile->device_table[dev_cnt];
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sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1];
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for (i = 0; i < sec_tbl->section_count; i++) {
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sec = (struct i40e_profile_section_header *)((u8 *)profile +
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sec_tbl->section_offset[i]);
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/* Skip 'AQ', 'note' and 'name' sections */
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if (sec->section.type != SECTION_TYPE_MMIO)
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continue;
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section_size = sec->section.size +
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sizeof(struct i40e_profile_section_header);
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/* Write profile */
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status = i40evf_aq_write_ddp(hw, (void *)sec, (u16)section_size,
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track_id, &offset, &info, NULL);
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if (status) {
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i40e_debug(hw, I40E_DEBUG_PACKAGE,
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"Failed to write profile: offset %d, info %d",
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offset, info);
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break;
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}
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}
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return status;
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}
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/**
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* i40evf_add_pinfo_to_list
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* @hw: pointer to the hardware structure
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* @profile: pointer to the profile segment of the package
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* @profile_info_sec: buffer for information section
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* @track_id: package tracking id
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*
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* Register a profile to the list of loaded profiles.
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*/
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enum i40e_status_code
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i40evf_add_pinfo_to_list(struct i40e_hw *hw,
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struct i40e_profile_segment *profile,
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u8 *profile_info_sec, u32 track_id)
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{
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i40e_status status = 0;
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struct i40e_profile_section_header *sec = NULL;
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struct i40e_profile_info *pinfo;
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u32 offset = 0, info = 0;
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sec = (struct i40e_profile_section_header *)profile_info_sec;
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sec->tbl_size = 1;
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sec->data_end = sizeof(struct i40e_profile_section_header) +
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sizeof(struct i40e_profile_info);
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sec->section.type = SECTION_TYPE_INFO;
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sec->section.offset = sizeof(struct i40e_profile_section_header);
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sec->section.size = sizeof(struct i40e_profile_info);
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pinfo = (struct i40e_profile_info *)(profile_info_sec +
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sec->section.offset);
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pinfo->track_id = track_id;
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pinfo->version = profile->version;
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pinfo->op = I40E_DDP_ADD_TRACKID;
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memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
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status = i40evf_aq_write_ddp(hw, (void *)sec, sec->data_end,
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track_id, &offset, &info, NULL);
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return status;
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}
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|
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@ -1,215 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright(c) 2013 - 2018 Intel Corporation. */
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#ifndef _I40E_HMC_H_
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#define _I40E_HMC_H_
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#define I40E_HMC_MAX_BP_COUNT 512
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/* forward-declare the HW struct for the compiler */
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struct i40e_hw;
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#define I40E_HMC_INFO_SIGNATURE 0x484D5347 /* HMSG */
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#define I40E_HMC_PD_CNT_IN_SD 512
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#define I40E_HMC_DIRECT_BP_SIZE 0x200000 /* 2M */
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#define I40E_HMC_PAGED_BP_SIZE 4096
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#define I40E_HMC_PD_BP_BUF_ALIGNMENT 4096
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#define I40E_FIRST_VF_FPM_ID 16
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struct i40e_hmc_obj_info {
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u64 base; /* base addr in FPM */
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u32 max_cnt; /* max count available for this hmc func */
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u32 cnt; /* count of objects driver actually wants to create */
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u64 size; /* size in bytes of one object */
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};
|
||||
|
||||
enum i40e_sd_entry_type {
|
||||
I40E_SD_TYPE_INVALID = 0,
|
||||
I40E_SD_TYPE_PAGED = 1,
|
||||
I40E_SD_TYPE_DIRECT = 2
|
||||
};
|
||||
|
||||
struct i40e_hmc_bp {
|
||||
enum i40e_sd_entry_type entry_type;
|
||||
struct i40e_dma_mem addr; /* populate to be used by hw */
|
||||
u32 sd_pd_index;
|
||||
u32 ref_cnt;
|
||||
};
|
||||
|
||||
struct i40e_hmc_pd_entry {
|
||||
struct i40e_hmc_bp bp;
|
||||
u32 sd_index;
|
||||
bool rsrc_pg;
|
||||
bool valid;
|
||||
};
|
||||
|
||||
struct i40e_hmc_pd_table {
|
||||
struct i40e_dma_mem pd_page_addr; /* populate to be used by hw */
|
||||
struct i40e_hmc_pd_entry *pd_entry; /* [512] for sw book keeping */
|
||||
struct i40e_virt_mem pd_entry_virt_mem; /* virt mem for pd_entry */
|
||||
|
||||
u32 ref_cnt;
|
||||
u32 sd_index;
|
||||
};
|
||||
|
||||
struct i40e_hmc_sd_entry {
|
||||
enum i40e_sd_entry_type entry_type;
|
||||
bool valid;
|
||||
|
||||
union {
|
||||
struct i40e_hmc_pd_table pd_table;
|
||||
struct i40e_hmc_bp bp;
|
||||
} u;
|
||||
};
|
||||
|
||||
struct i40e_hmc_sd_table {
|
||||
struct i40e_virt_mem addr; /* used to track sd_entry allocations */
|
||||
u32 sd_cnt;
|
||||
u32 ref_cnt;
|
||||
struct i40e_hmc_sd_entry *sd_entry; /* (sd_cnt*512) entries max */
|
||||
};
|
||||
|
||||
struct i40e_hmc_info {
|
||||
u32 signature;
|
||||
/* equals to pci func num for PF and dynamically allocated for VFs */
|
||||
u8 hmc_fn_id;
|
||||
u16 first_sd_index; /* index of the first available SD */
|
||||
|
||||
/* hmc objects */
|
||||
struct i40e_hmc_obj_info *hmc_obj;
|
||||
struct i40e_virt_mem hmc_obj_virt_mem;
|
||||
struct i40e_hmc_sd_table sd_table;
|
||||
};
|
||||
|
||||
#define I40E_INC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt++)
|
||||
#define I40E_INC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt++)
|
||||
#define I40E_INC_BP_REFCNT(bp) ((bp)->ref_cnt++)
|
||||
|
||||
#define I40E_DEC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt--)
|
||||
#define I40E_DEC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt--)
|
||||
#define I40E_DEC_BP_REFCNT(bp) ((bp)->ref_cnt--)
|
||||
|
||||
/**
|
||||
* I40E_SET_PF_SD_ENTRY - marks the sd entry as valid in the hardware
|
||||
* @hw: pointer to our hw struct
|
||||
* @pa: pointer to physical address
|
||||
* @sd_index: segment descriptor index
|
||||
* @type: if sd entry is direct or paged
|
||||
**/
|
||||
#define I40E_SET_PF_SD_ENTRY(hw, pa, sd_index, type) \
|
||||
{ \
|
||||
u32 val1, val2, val3; \
|
||||
val1 = (u32)(upper_32_bits(pa)); \
|
||||
val2 = (u32)(pa) | (I40E_HMC_MAX_BP_COUNT << \
|
||||
I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \
|
||||
((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \
|
||||
I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) | \
|
||||
BIT(I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT); \
|
||||
val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
|
||||
wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \
|
||||
wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
|
||||
wr32((hw), I40E_PFHMC_SDCMD, val3); \
|
||||
}
|
||||
|
||||
/**
|
||||
* I40E_CLEAR_PF_SD_ENTRY - marks the sd entry as invalid in the hardware
|
||||
* @hw: pointer to our hw struct
|
||||
* @sd_index: segment descriptor index
|
||||
* @type: if sd entry is direct or paged
|
||||
**/
|
||||
#define I40E_CLEAR_PF_SD_ENTRY(hw, sd_index, type) \
|
||||
{ \
|
||||
u32 val2, val3; \
|
||||
val2 = (I40E_HMC_MAX_BP_COUNT << \
|
||||
I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \
|
||||
((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \
|
||||
I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT); \
|
||||
val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
|
||||
wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \
|
||||
wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
|
||||
wr32((hw), I40E_PFHMC_SDCMD, val3); \
|
||||
}
|
||||
|
||||
/**
|
||||
* I40E_INVALIDATE_PF_HMC_PD - Invalidates the pd cache in the hardware
|
||||
* @hw: pointer to our hw struct
|
||||
* @sd_idx: segment descriptor index
|
||||
* @pd_idx: page descriptor index
|
||||
**/
|
||||
#define I40E_INVALIDATE_PF_HMC_PD(hw, sd_idx, pd_idx) \
|
||||
wr32((hw), I40E_PFHMC_PDINV, \
|
||||
(((sd_idx) << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) | \
|
||||
((pd_idx) << I40E_PFHMC_PDINV_PMPDIDX_SHIFT)))
|
||||
|
||||
/**
|
||||
* I40E_FIND_SD_INDEX_LIMIT - finds segment descriptor index limit
|
||||
* @hmc_info: pointer to the HMC configuration information structure
|
||||
* @type: type of HMC resources we're searching
|
||||
* @index: starting index for the object
|
||||
* @cnt: number of objects we're trying to create
|
||||
* @sd_idx: pointer to return index of the segment descriptor in question
|
||||
* @sd_limit: pointer to return the maximum number of segment descriptors
|
||||
*
|
||||
* This function calculates the segment descriptor index and index limit
|
||||
* for the resource defined by i40e_hmc_rsrc_type.
|
||||
**/
|
||||
#define I40E_FIND_SD_INDEX_LIMIT(hmc_info, type, index, cnt, sd_idx, sd_limit)\
|
||||
{ \
|
||||
u64 fpm_addr, fpm_limit; \
|
||||
fpm_addr = (hmc_info)->hmc_obj[(type)].base + \
|
||||
(hmc_info)->hmc_obj[(type)].size * (index); \
|
||||
fpm_limit = fpm_addr + (hmc_info)->hmc_obj[(type)].size * (cnt);\
|
||||
*(sd_idx) = (u32)(fpm_addr / I40E_HMC_DIRECT_BP_SIZE); \
|
||||
*(sd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_DIRECT_BP_SIZE); \
|
||||
/* add one more to the limit to correct our range */ \
|
||||
*(sd_limit) += 1; \
|
||||
}
|
||||
|
||||
/**
|
||||
* I40E_FIND_PD_INDEX_LIMIT - finds page descriptor index limit
|
||||
* @hmc_info: pointer to the HMC configuration information struct
|
||||
* @type: HMC resource type we're examining
|
||||
* @idx: starting index for the object
|
||||
* @cnt: number of objects we're trying to create
|
||||
* @pd_index: pointer to return page descriptor index
|
||||
* @pd_limit: pointer to return page descriptor index limit
|
||||
*
|
||||
* Calculates the page descriptor index and index limit for the resource
|
||||
* defined by i40e_hmc_rsrc_type.
|
||||
**/
|
||||
#define I40E_FIND_PD_INDEX_LIMIT(hmc_info, type, idx, cnt, pd_index, pd_limit)\
|
||||
{ \
|
||||
u64 fpm_adr, fpm_limit; \
|
||||
fpm_adr = (hmc_info)->hmc_obj[(type)].base + \
|
||||
(hmc_info)->hmc_obj[(type)].size * (idx); \
|
||||
fpm_limit = fpm_adr + (hmc_info)->hmc_obj[(type)].size * (cnt); \
|
||||
*(pd_index) = (u32)(fpm_adr / I40E_HMC_PAGED_BP_SIZE); \
|
||||
*(pd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_PAGED_BP_SIZE); \
|
||||
/* add one more to the limit to correct our range */ \
|
||||
*(pd_limit) += 1; \
|
||||
}
|
||||
i40e_status i40e_add_sd_table_entry(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 sd_index,
|
||||
enum i40e_sd_entry_type type,
|
||||
u64 direct_mode_sz);
|
||||
|
||||
i40e_status i40e_add_pd_table_entry(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 pd_index,
|
||||
struct i40e_dma_mem *rsrc_pg);
|
||||
i40e_status i40e_remove_pd_bp(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx);
|
||||
i40e_status i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info,
|
||||
u32 idx);
|
||||
i40e_status i40e_remove_sd_bp_new(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx, bool is_pf);
|
||||
i40e_status i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info,
|
||||
u32 idx);
|
||||
i40e_status i40e_remove_pd_page_new(struct i40e_hw *hw,
|
||||
struct i40e_hmc_info *hmc_info,
|
||||
u32 idx, bool is_pf);
|
||||
|
||||
#endif /* _I40E_HMC_H_ */
|
||||
|
|
@ -1,158 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright(c) 2013 - 2018 Intel Corporation. */
|
||||
|
||||
#ifndef _I40E_LAN_HMC_H_
|
||||
#define _I40E_LAN_HMC_H_
|
||||
|
||||
/* forward-declare the HW struct for the compiler */
|
||||
struct i40e_hw;
|
||||
|
||||
/* HMC element context information */
|
||||
|
||||
/* Rx queue context data
|
||||
*
|
||||
* The sizes of the variables may be larger than needed due to crossing byte
|
||||
* boundaries. If we do not have the width of the variable set to the correct
|
||||
* size then we could end up shifting bits off the top of the variable when the
|
||||
* variable is at the top of a byte and crosses over into the next byte.
|
||||
*/
|
||||
struct i40e_hmc_obj_rxq {
|
||||
u16 head;
|
||||
u16 cpuid; /* bigger than needed, see above for reason */
|
||||
u64 base;
|
||||
u16 qlen;
|
||||
#define I40E_RXQ_CTX_DBUFF_SHIFT 7
|
||||
u16 dbuff; /* bigger than needed, see above for reason */
|
||||
#define I40E_RXQ_CTX_HBUFF_SHIFT 6
|
||||
u16 hbuff; /* bigger than needed, see above for reason */
|
||||
u8 dtype;
|
||||
u8 dsize;
|
||||
u8 crcstrip;
|
||||
u8 fc_ena;
|
||||
u8 l2tsel;
|
||||
u8 hsplit_0;
|
||||
u8 hsplit_1;
|
||||
u8 showiv;
|
||||
u32 rxmax; /* bigger than needed, see above for reason */
|
||||
u8 tphrdesc_ena;
|
||||
u8 tphwdesc_ena;
|
||||
u8 tphdata_ena;
|
||||
u8 tphhead_ena;
|
||||
u16 lrxqthresh; /* bigger than needed, see above for reason */
|
||||
u8 prefena; /* NOTE: normally must be set to 1 at init */
|
||||
};
|
||||
|
||||
/* Tx queue context data
|
||||
*
|
||||
* The sizes of the variables may be larger than needed due to crossing byte
|
||||
* boundaries. If we do not have the width of the variable set to the correct
|
||||
* size then we could end up shifting bits off the top of the variable when the
|
||||
* variable is at the top of a byte and crosses over into the next byte.
|
||||
*/
|
||||
struct i40e_hmc_obj_txq {
|
||||
u16 head;
|
||||
u8 new_context;
|
||||
u64 base;
|
||||
u8 fc_ena;
|
||||
u8 timesync_ena;
|
||||
u8 fd_ena;
|
||||
u8 alt_vlan_ena;
|
||||
u16 thead_wb;
|
||||
u8 cpuid;
|
||||
u8 head_wb_ena;
|
||||
u16 qlen;
|
||||
u8 tphrdesc_ena;
|
||||
u8 tphrpacket_ena;
|
||||
u8 tphwdesc_ena;
|
||||
u64 head_wb_addr;
|
||||
u32 crc;
|
||||
u16 rdylist;
|
||||
u8 rdylist_act;
|
||||
};
|
||||
|
||||
/* for hsplit_0 field of Rx HMC context */
|
||||
enum i40e_hmc_obj_rx_hsplit_0 {
|
||||
I40E_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT = 0,
|
||||
I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2 = 1,
|
||||
I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP = 2,
|
||||
I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP = 4,
|
||||
I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP = 8,
|
||||
};
|
||||
|
||||
/* fcoe_cntx and fcoe_filt are for debugging purpose only */
|
||||
struct i40e_hmc_obj_fcoe_cntx {
|
||||
u32 rsv[32];
|
||||
};
|
||||
|
||||
struct i40e_hmc_obj_fcoe_filt {
|
||||
u32 rsv[8];
|
||||
};
|
||||
|
||||
/* Context sizes for LAN objects */
|
||||
enum i40e_hmc_lan_object_size {
|
||||
I40E_HMC_LAN_OBJ_SZ_8 = 0x3,
|
||||
I40E_HMC_LAN_OBJ_SZ_16 = 0x4,
|
||||
I40E_HMC_LAN_OBJ_SZ_32 = 0x5,
|
||||
I40E_HMC_LAN_OBJ_SZ_64 = 0x6,
|
||||
I40E_HMC_LAN_OBJ_SZ_128 = 0x7,
|
||||
I40E_HMC_LAN_OBJ_SZ_256 = 0x8,
|
||||
I40E_HMC_LAN_OBJ_SZ_512 = 0x9,
|
||||
};
|
||||
|
||||
#define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512
|
||||
#define I40E_HMC_OBJ_SIZE_TXQ 128
|
||||
#define I40E_HMC_OBJ_SIZE_RXQ 32
|
||||
#define I40E_HMC_OBJ_SIZE_FCOE_CNTX 128
|
||||
#define I40E_HMC_OBJ_SIZE_FCOE_FILT 64
|
||||
|
||||
enum i40e_hmc_lan_rsrc_type {
|
||||
I40E_HMC_LAN_FULL = 0,
|
||||
I40E_HMC_LAN_TX = 1,
|
||||
I40E_HMC_LAN_RX = 2,
|
||||
I40E_HMC_FCOE_CTX = 3,
|
||||
I40E_HMC_FCOE_FILT = 4,
|
||||
I40E_HMC_LAN_MAX = 5
|
||||
};
|
||||
|
||||
enum i40e_hmc_model {
|
||||
I40E_HMC_MODEL_DIRECT_PREFERRED = 0,
|
||||
I40E_HMC_MODEL_DIRECT_ONLY = 1,
|
||||
I40E_HMC_MODEL_PAGED_ONLY = 2,
|
||||
I40E_HMC_MODEL_UNKNOWN,
|
||||
};
|
||||
|
||||
struct i40e_hmc_lan_create_obj_info {
|
||||
struct i40e_hmc_info *hmc_info;
|
||||
u32 rsrc_type;
|
||||
u32 start_idx;
|
||||
u32 count;
|
||||
enum i40e_sd_entry_type entry_type;
|
||||
u64 direct_mode_sz;
|
||||
};
|
||||
|
||||
struct i40e_hmc_lan_delete_obj_info {
|
||||
struct i40e_hmc_info *hmc_info;
|
||||
u32 rsrc_type;
|
||||
u32 start_idx;
|
||||
u32 count;
|
||||
};
|
||||
|
||||
i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
|
||||
u32 rxq_num, u32 fcoe_cntx_num,
|
||||
u32 fcoe_filt_num);
|
||||
i40e_status i40e_configure_lan_hmc(struct i40e_hw *hw,
|
||||
enum i40e_hmc_model model);
|
||||
i40e_status i40e_shutdown_lan_hmc(struct i40e_hw *hw);
|
||||
|
||||
i40e_status i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue);
|
||||
i40e_status i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue,
|
||||
struct i40e_hmc_obj_txq *s);
|
||||
i40e_status i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue);
|
||||
i40e_status i40e_set_lan_rx_queue_context(struct i40e_hw *hw,
|
||||
u16 queue,
|
||||
struct i40e_hmc_obj_rxq *s);
|
||||
|
||||
#endif /* _I40E_LAN_HMC_H_ */
|
||||
|
|
@ -60,71 +60,12 @@ static inline struct i40e_rx_ptype_decoded decode_rx_desc_ptype(u8 ptype)
|
|||
return i40evf_ptype_lookup[ptype];
|
||||
}
|
||||
|
||||
/* prototype for functions used for SW locks */
|
||||
|
||||
/* i40e_common for VF drivers*/
|
||||
void i40e_vf_parse_hw_config(struct i40e_hw *hw,
|
||||
struct virtchnl_vf_resource *msg);
|
||||
i40e_status i40e_vf_reset(struct i40e_hw *hw);
|
||||
i40e_status i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
|
||||
enum virtchnl_ops v_opcode,
|
||||
i40e_status v_retval,
|
||||
u8 *msg, u16 msglen,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_set_filter_control(struct i40e_hw *hw,
|
||||
struct i40e_filter_control_settings *settings);
|
||||
i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
|
||||
u8 *mac_addr, u16 ethtype, u16 flags,
|
||||
u16 vsi_seid, u16 queue, bool is_add,
|
||||
struct i40e_control_filter_stats *stats,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
|
||||
u16 vsi_seid);
|
||||
i40e_status i40evf_aq_rx_ctl_read_register(struct i40e_hw *hw,
|
||||
u32 reg_addr, u32 *reg_val,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
u32 i40evf_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr);
|
||||
i40e_status i40evf_aq_rx_ctl_write_register(struct i40e_hw *hw,
|
||||
u32 reg_addr, u32 reg_val,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
void i40evf_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val);
|
||||
i40e_status i40e_aq_set_phy_register(struct i40e_hw *hw,
|
||||
u8 phy_select, u8 dev_addr,
|
||||
u32 reg_addr, u32 reg_val,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
i40e_status i40e_aq_get_phy_register(struct i40e_hw *hw,
|
||||
u8 phy_select, u8 dev_addr,
|
||||
u32 reg_addr, u32 *reg_val,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
|
||||
i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page,
|
||||
u16 reg, u8 phy_addr, u16 *value);
|
||||
i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page,
|
||||
u16 reg, u8 phy_addr, u16 value);
|
||||
i40e_status i40e_read_phy_register(struct i40e_hw *hw, u8 page, u16 reg,
|
||||
u8 phy_addr, u16 *value);
|
||||
i40e_status i40e_write_phy_register(struct i40e_hw *hw, u8 page, u16 reg,
|
||||
u8 phy_addr, u16 value);
|
||||
u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num);
|
||||
i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
|
||||
u32 time, u32 interval);
|
||||
i40e_status i40evf_aq_write_ddp(struct i40e_hw *hw, void *buff,
|
||||
u16 buff_size, u32 track_id,
|
||||
u32 *error_offset, u32 *error_info,
|
||||
struct i40e_asq_cmd_details *
|
||||
cmd_details);
|
||||
i40e_status i40evf_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
|
||||
u16 buff_size, u8 flags,
|
||||
struct i40e_asq_cmd_details *
|
||||
cmd_details);
|
||||
struct i40e_generic_seg_header *
|
||||
i40evf_find_segment_in_package(u32 segment_type,
|
||||
struct i40e_package_header *pkg_header);
|
||||
enum i40e_status_code
|
||||
i40evf_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *i40e_seg,
|
||||
u32 track_id);
|
||||
enum i40e_status_code
|
||||
i40evf_add_pinfo_to_list(struct i40e_hw *hw,
|
||||
struct i40e_profile_segment *profile,
|
||||
u8 *profile_info_sec, u32 track_id);
|
||||
enum virtchnl_ops v_opcode,
|
||||
i40e_status v_retval, u8 *msg, u16 msglen,
|
||||
struct i40e_asq_cmd_details *cmd_details);
|
||||
#endif /* _I40E_PROTOTYPE_H_ */
|
||||
|
|
|
|||
|
|
@ -4,40 +4,12 @@
|
|||
#ifndef _I40E_REGISTER_H_
|
||||
#define _I40E_REGISTER_H_
|
||||
|
||||
#define I40E_VFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */
|
||||
#define I40E_VFMSIX_PBA1_MAX_INDEX 19
|
||||
#define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0
|
||||
#define I40E_VFMSIX_PBA1_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA1_PENBIT_SHIFT)
|
||||
#define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
|
||||
#define I40E_VFMSIX_TADD1_MAX_INDEX 639
|
||||
#define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0
|
||||
#define I40E_VFMSIX_TADD1_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT)
|
||||
#define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT 2
|
||||
#define I40E_VFMSIX_TADD1_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD1_MSIXTADD_SHIFT)
|
||||
#define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
|
||||
#define I40E_VFMSIX_TMSG1_MAX_INDEX 639
|
||||
#define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0
|
||||
#define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT)
|
||||
#define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
|
||||
#define I40E_VFMSIX_TUADD1_MAX_INDEX 639
|
||||
#define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0
|
||||
#define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT)
|
||||
#define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
|
||||
#define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639
|
||||
#define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0
|
||||
#define I40E_VFMSIX_TVCTRL1_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL1_MASK_SHIFT)
|
||||
#define I40E_VF_ARQBAH1 0x00006000 /* Reset: EMPR */
|
||||
#define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0
|
||||
#define I40E_VF_ARQBAH1_ARQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAH1_ARQBAH_SHIFT)
|
||||
#define I40E_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */
|
||||
#define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0
|
||||
#define I40E_VF_ARQBAL1_ARQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ARQBAL1_ARQBAL_SHIFT)
|
||||
#define I40E_VF_ARQH1 0x00007400 /* Reset: EMPR */
|
||||
#define I40E_VF_ARQH1_ARQH_SHIFT 0
|
||||
#define I40E_VF_ARQH1_ARQH_MASK I40E_MASK(0x3FF, I40E_VF_ARQH1_ARQH_SHIFT)
|
||||
#define I40E_VF_ARQLEN1 0x00008000 /* Reset: EMPR */
|
||||
#define I40E_VF_ARQLEN1_ARQLEN_SHIFT 0
|
||||
#define I40E_VF_ARQLEN1_ARQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ARQLEN1_ARQLEN_SHIFT)
|
||||
#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28
|
||||
#define I40E_VF_ARQLEN1_ARQVFE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQVFE_SHIFT)
|
||||
#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29
|
||||
|
|
@ -47,20 +19,10 @@
|
|||
#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31
|
||||
#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)
|
||||
#define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */
|
||||
#define I40E_VF_ARQT1_ARQT_SHIFT 0
|
||||
#define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT)
|
||||
#define I40E_VF_ATQBAH1 0x00007800 /* Reset: EMPR */
|
||||
#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0
|
||||
#define I40E_VF_ATQBAH1_ATQBAH_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAH1_ATQBAH_SHIFT)
|
||||
#define I40E_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */
|
||||
#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0
|
||||
#define I40E_VF_ATQBAL1_ATQBAL_MASK I40E_MASK(0xFFFFFFFF, I40E_VF_ATQBAL1_ATQBAL_SHIFT)
|
||||
#define I40E_VF_ATQH1 0x00006400 /* Reset: EMPR */
|
||||
#define I40E_VF_ATQH1_ATQH_SHIFT 0
|
||||
#define I40E_VF_ATQH1_ATQH_MASK I40E_MASK(0x3FF, I40E_VF_ATQH1_ATQH_SHIFT)
|
||||
#define I40E_VF_ATQLEN1 0x00006800 /* Reset: EMPR */
|
||||
#define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0
|
||||
#define I40E_VF_ATQLEN1_ATQLEN_MASK I40E_MASK(0x3FF, I40E_VF_ATQLEN1_ATQLEN_SHIFT)
|
||||
#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28
|
||||
#define I40E_VF_ATQLEN1_ATQVFE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQVFE_SHIFT)
|
||||
#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29
|
||||
|
|
@ -70,244 +32,37 @@
|
|||
#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31
|
||||
#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)
|
||||
#define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */
|
||||
#define I40E_VF_ATQT1_ATQT_SHIFT 0
|
||||
#define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT)
|
||||
#define I40E_VFGEN_RSTAT 0x00008800 /* Reset: VFR */
|
||||
#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0
|
||||
#define I40E_VFGEN_RSTAT_VFR_STATE_MASK I40E_MASK(0x3, I40E_VFGEN_RSTAT_VFR_STATE_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */
|
||||
#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0
|
||||
#define I40E_VFINT_DYN_CTL01_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1
|
||||
#define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2
|
||||
#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3
|
||||
#define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT 5
|
||||
#define I40E_VFINT_DYN_CTL01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24
|
||||
#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25
|
||||
#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT 31
|
||||
#define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */
|
||||
#define I40E_VFINT_DYN_CTLN1_MAX_INDEX 15
|
||||
#define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0
|
||||
#define I40E_VFINT_DYN_CTLN1_INTENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1
|
||||
#define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2
|
||||
#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3
|
||||
#define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5
|
||||
#define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24
|
||||
#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25
|
||||
#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31
|
||||
#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT)
|
||||
#define I40E_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */
|
||||
#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25
|
||||
#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT)
|
||||
#define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30
|
||||
#define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT)
|
||||
#define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31
|
||||
#define I40E_VFINT_ICR0_ENA1_RSVD_MASK I40E_MASK(0x1, I40E_VFINT_ICR0_ENA1_RSVD_SHIFT)
|
||||
#define I40E_VFINT_ICR01 0x00004800 /* Reset: CORER */
|
||||
#define I40E_VFINT_ICR01_INTEVENT_SHIFT 0
|
||||
#define I40E_VFINT_ICR01_INTEVENT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_INTEVENT_SHIFT)
|
||||
#define I40E_VFINT_ICR01_QUEUE_0_SHIFT 1
|
||||
#define I40E_VFINT_ICR01_QUEUE_0_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_0_SHIFT)
|
||||
#define I40E_VFINT_ICR01_QUEUE_1_SHIFT 2
|
||||
#define I40E_VFINT_ICR01_QUEUE_1_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_1_SHIFT)
|
||||
#define I40E_VFINT_ICR01_QUEUE_2_SHIFT 3
|
||||
#define I40E_VFINT_ICR01_QUEUE_2_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_2_SHIFT)
|
||||
#define I40E_VFINT_ICR01_QUEUE_3_SHIFT 4
|
||||
#define I40E_VFINT_ICR01_QUEUE_3_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_QUEUE_3_SHIFT)
|
||||
#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25
|
||||
#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT)
|
||||
#define I40E_VFINT_ICR01_ADMINQ_SHIFT 30
|
||||
#define I40E_VFINT_ICR01_ADMINQ_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_ADMINQ_SHIFT)
|
||||
#define I40E_VFINT_ICR01_SWINT_SHIFT 31
|
||||
#define I40E_VFINT_ICR01_SWINT_MASK I40E_MASK(0x1, I40E_VFINT_ICR01_SWINT_SHIFT)
|
||||
#define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */
|
||||
#define I40E_VFINT_ITR01_MAX_INDEX 2
|
||||
#define I40E_VFINT_ITR01_INTERVAL_SHIFT 0
|
||||
#define I40E_VFINT_ITR01_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITR01_INTERVAL_SHIFT)
|
||||
#define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */
|
||||
#define I40E_VFINT_ITRN1_MAX_INDEX 2
|
||||
#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0
|
||||
#define I40E_VFINT_ITRN1_INTERVAL_MASK I40E_MASK(0xFFF, I40E_VFINT_ITRN1_INTERVAL_SHIFT)
|
||||
#define I40E_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */
|
||||
#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2
|
||||
#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK I40E_MASK(0x3, I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT)
|
||||
#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */
|
||||
#define I40E_QRX_TAIL1_MAX_INDEX 15
|
||||
#define I40E_QRX_TAIL1_TAIL_SHIFT 0
|
||||
#define I40E_QRX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QRX_TAIL1_TAIL_SHIFT)
|
||||
#define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */
|
||||
#define I40E_QTX_TAIL1_MAX_INDEX 15
|
||||
#define I40E_QTX_TAIL1_TAIL_SHIFT 0
|
||||
#define I40E_QTX_TAIL1_TAIL_MASK I40E_MASK(0x1FFF, I40E_QTX_TAIL1_TAIL_SHIFT)
|
||||
#define I40E_VFMSIX_PBA 0x00002000 /* Reset: VFLR */
|
||||
#define I40E_VFMSIX_PBA_PENBIT_SHIFT 0
|
||||
#define I40E_VFMSIX_PBA_PENBIT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_PBA_PENBIT_SHIFT)
|
||||
#define I40E_VFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
|
||||
#define I40E_VFMSIX_TADD_MAX_INDEX 16
|
||||
#define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0
|
||||
#define I40E_VFMSIX_TADD_MSIXTADD10_MASK I40E_MASK(0x3, I40E_VFMSIX_TADD_MSIXTADD10_SHIFT)
|
||||
#define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2
|
||||
#define I40E_VFMSIX_TADD_MSIXTADD_MASK I40E_MASK(0x3FFFFFFF, I40E_VFMSIX_TADD_MSIXTADD_SHIFT)
|
||||
#define I40E_VFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
|
||||
#define I40E_VFMSIX_TMSG_MAX_INDEX 16
|
||||
#define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0
|
||||
#define I40E_VFMSIX_TMSG_MSIXTMSG_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT)
|
||||
#define I40E_VFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
|
||||
#define I40E_VFMSIX_TUADD_MAX_INDEX 16
|
||||
#define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0
|
||||
#define I40E_VFMSIX_TUADD_MSIXTUADD_MASK I40E_MASK(0xFFFFFFFF, I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT)
|
||||
#define I40E_VFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
|
||||
#define I40E_VFMSIX_TVCTRL_MAX_INDEX 16
|
||||
#define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0
|
||||
#define I40E_VFMSIX_TVCTRL_MASK_MASK I40E_MASK(0x1, I40E_VFMSIX_TVCTRL_MASK_SHIFT)
|
||||
#define I40E_VFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */
|
||||
#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0
|
||||
#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK I40E_MASK(0xF, I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT)
|
||||
#define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT 4
|
||||
#define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT)
|
||||
#define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT 8
|
||||
#define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK I40E_MASK(0x3FFFF, I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT)
|
||||
#define I40E_VFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */
|
||||
#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0
|
||||
#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK I40E_MASK(0x1, I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT)
|
||||
#define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT 4
|
||||
#define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK I40E_MASK(0x7, I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT)
|
||||
#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8
|
||||
#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)
|
||||
#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16
|
||||
#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)
|
||||
#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24
|
||||
#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)
|
||||
#define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
|
||||
#define I40E_VFQF_HENA_MAX_INDEX 1
|
||||
#define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0
|
||||
#define I40E_VFQF_HENA_PTYPE_ENA_MASK I40E_MASK(0xFFFFFFFF, I40E_VFQF_HENA_PTYPE_ENA_SHIFT)
|
||||
#define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */
|
||||
#define I40E_VFQF_HKEY_MAX_INDEX 12
|
||||
#define I40E_VFQF_HKEY_KEY_0_SHIFT 0
|
||||
#define I40E_VFQF_HKEY_KEY_0_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_0_SHIFT)
|
||||
#define I40E_VFQF_HKEY_KEY_1_SHIFT 8
|
||||
#define I40E_VFQF_HKEY_KEY_1_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_1_SHIFT)
|
||||
#define I40E_VFQF_HKEY_KEY_2_SHIFT 16
|
||||
#define I40E_VFQF_HKEY_KEY_2_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_2_SHIFT)
|
||||
#define I40E_VFQF_HKEY_KEY_3_SHIFT 24
|
||||
#define I40E_VFQF_HKEY_KEY_3_MASK I40E_MASK(0xFF, I40E_VFQF_HKEY_KEY_3_SHIFT)
|
||||
#define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
|
||||
#define I40E_VFQF_HLUT_MAX_INDEX 15
|
||||
#define I40E_VFQF_HLUT_LUT0_SHIFT 0
|
||||
#define I40E_VFQF_HLUT_LUT0_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT0_SHIFT)
|
||||
#define I40E_VFQF_HLUT_LUT1_SHIFT 8
|
||||
#define I40E_VFQF_HLUT_LUT1_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT1_SHIFT)
|
||||
#define I40E_VFQF_HLUT_LUT2_SHIFT 16
|
||||
#define I40E_VFQF_HLUT_LUT2_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT2_SHIFT)
|
||||
#define I40E_VFQF_HLUT_LUT3_SHIFT 24
|
||||
#define I40E_VFQF_HLUT_LUT3_MASK I40E_MASK(0xF, I40E_VFQF_HLUT_LUT3_SHIFT)
|
||||
#define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
|
||||
#define I40E_VFQF_HREGION_MAX_INDEX 7
|
||||
#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0
|
||||
#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
|
||||
#define I40E_VFQF_HREGION_REGION_0_SHIFT 1
|
||||
#define I40E_VFQF_HREGION_REGION_0_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_0_SHIFT)
|
||||
#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4
|
||||
#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
|
||||
#define I40E_VFQF_HREGION_REGION_1_SHIFT 5
|
||||
#define I40E_VFQF_HREGION_REGION_1_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_1_SHIFT)
|
||||
#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8
|
||||
#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
|
||||
#define I40E_VFQF_HREGION_REGION_2_SHIFT 9
|
||||
#define I40E_VFQF_HREGION_REGION_2_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_2_SHIFT)
|
||||
#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12
|
||||
#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
|
||||
#define I40E_VFQF_HREGION_REGION_3_SHIFT 13
|
||||
#define I40E_VFQF_HREGION_REGION_3_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_3_SHIFT)
|
||||
#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16
|
||||
#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
|
||||
#define I40E_VFQF_HREGION_REGION_4_SHIFT 17
|
||||
#define I40E_VFQF_HREGION_REGION_4_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_4_SHIFT)
|
||||
#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20
|
||||
#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
|
||||
#define I40E_VFQF_HREGION_REGION_5_SHIFT 21
|
||||
#define I40E_VFQF_HREGION_REGION_5_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_5_SHIFT)
|
||||
#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24
|
||||
#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
|
||||
#define I40E_VFQF_HREGION_REGION_6_SHIFT 25
|
||||
#define I40E_VFQF_HREGION_REGION_6_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_6_SHIFT)
|
||||
#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28
|
||||
#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK I40E_MASK(0x1, I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
|
||||
#define I40E_VFQF_HREGION_REGION_7_SHIFT 29
|
||||
#define I40E_VFQF_HREGION_REGION_7_MASK I40E_MASK(0x7, I40E_VFQF_HREGION_REGION_7_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30
|
||||
#define I40E_VFINT_DYN_CTL01_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTL01_WB_ON_ITR_SHIFT)
|
||||
#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30
|
||||
#define I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK I40E_MASK(0x1, I40E_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)
|
||||
#define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */
|
||||
#define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0
|
||||
#define I40E_VFPE_AEQALLOC1_AECOUNT_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT)
|
||||
#define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */
|
||||
#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0
|
||||
#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT)
|
||||
#define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */
|
||||
#define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0
|
||||
#define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT)
|
||||
#define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */
|
||||
#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0
|
||||
#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT)
|
||||
#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4
|
||||
#define I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_MASK I40E_MASK(0x7, I40E_VFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT)
|
||||
#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16
|
||||
#define I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK I40E_MASK(0x3F, I40E_VFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT)
|
||||
#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31
|
||||
#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT)
|
||||
#define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */
|
||||
#define I40E_VFPE_CQACK1_PECQID_SHIFT 0
|
||||
#define I40E_VFPE_CQACK1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQACK1_PECQID_SHIFT)
|
||||
#define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */
|
||||
#define I40E_VFPE_CQARM1_PECQID_SHIFT 0
|
||||
#define I40E_VFPE_CQARM1_PECQID_MASK I40E_MASK(0x1FFFF, I40E_VFPE_CQARM1_PECQID_SHIFT)
|
||||
#define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */
|
||||
#define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0
|
||||
#define I40E_VFPE_CQPDB1_WQHEAD_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPDB1_WQHEAD_SHIFT)
|
||||
#define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */
|
||||
#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0
|
||||
#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT)
|
||||
#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16
|
||||
#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK I40E_MASK(0xFFFF, I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT)
|
||||
#define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */
|
||||
#define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0
|
||||
#define I40E_VFPE_CQPTAIL1_WQTAIL_MASK I40E_MASK(0x7FF, I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT)
|
||||
#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31
|
||||
#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK I40E_MASK(0x1, I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT)
|
||||
#define I40E_VFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */
|
||||
#define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0
|
||||
#define I40E_VFPE_IPCONFIG01_PEIPID_MASK I40E_MASK(0xFFFF, I40E_VFPE_IPCONFIG01_PEIPID_SHIFT)
|
||||
#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16
|
||||
#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK I40E_MASK(0x1, I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT)
|
||||
#define I40E_VFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */
|
||||
#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0
|
||||
#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK I40E_MASK(0x1F, I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT)
|
||||
#define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */
|
||||
#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0
|
||||
#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK I40E_MASK(0xFFFFFF, I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT)
|
||||
#define I40E_VFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */
|
||||
#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0
|
||||
#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK I40E_MASK(0xFFFFFFFF, I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT)
|
||||
#define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */
|
||||
#define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0
|
||||
#define I40E_VFPE_WQEALLOC1_PEQPID_MASK I40E_MASK(0x3FFFF, I40E_VFPE_WQEALLOC1_PEQPID_SHIFT)
|
||||
#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20
|
||||
#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK I40E_MASK(0xFFF, I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT)
|
||||
#endif /* _I40E_REGISTER_H_ */
|
||||
|
|
|
|||
|
|
@ -8,26 +8,16 @@
|
|||
#include "i40e_osdep.h"
|
||||
#include "i40e_register.h"
|
||||
#include "i40e_adminq.h"
|
||||
#include "i40e_hmc.h"
|
||||
#include "i40e_lan_hmc.h"
|
||||
#include "i40e_devids.h"
|
||||
|
||||
#define I40E_RXQ_CTX_DBUFF_SHIFT 7
|
||||
|
||||
/* I40E_MASK is a macro used on 32 bit registers */
|
||||
#define I40E_MASK(mask, shift) ((u32)(mask) << (shift))
|
||||
|
||||
#define I40E_MAX_VSI_QP 16
|
||||
#define I40E_MAX_VF_VSI 3
|
||||
#define I40E_MAX_CHAINED_RX_BUFFERS 5
|
||||
#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
|
||||
|
||||
/* Max default timeout in ms, */
|
||||
#define I40E_MAX_NVM_TIMEOUT 18000
|
||||
|
||||
/* Max timeout in ms for the phy to respond */
|
||||
#define I40E_MAX_PHY_TIMEOUT 500
|
||||
|
||||
/* Switch from ms to the 1usec global time (this is the GTIME resolution) */
|
||||
#define I40E_MS_TO_GTIME(time) ((time) * 1000)
|
||||
|
||||
/* forward declaration */
|
||||
struct i40e_hw;
|
||||
|
|
@ -88,33 +78,6 @@ enum i40e_mac_type {
|
|||
I40E_MAC_GENERIC,
|
||||
};
|
||||
|
||||
enum i40e_media_type {
|
||||
I40E_MEDIA_TYPE_UNKNOWN = 0,
|
||||
I40E_MEDIA_TYPE_FIBER,
|
||||
I40E_MEDIA_TYPE_BASET,
|
||||
I40E_MEDIA_TYPE_BACKPLANE,
|
||||
I40E_MEDIA_TYPE_CX4,
|
||||
I40E_MEDIA_TYPE_DA,
|
||||
I40E_MEDIA_TYPE_VIRTUAL
|
||||
};
|
||||
|
||||
enum i40e_fc_mode {
|
||||
I40E_FC_NONE = 0,
|
||||
I40E_FC_RX_PAUSE,
|
||||
I40E_FC_TX_PAUSE,
|
||||
I40E_FC_FULL,
|
||||
I40E_FC_PFC,
|
||||
I40E_FC_DEFAULT
|
||||
};
|
||||
|
||||
enum i40e_set_fc_aq_failures {
|
||||
I40E_SET_FC_AQ_FAIL_NONE = 0,
|
||||
I40E_SET_FC_AQ_FAIL_GET = 1,
|
||||
I40E_SET_FC_AQ_FAIL_SET = 2,
|
||||
I40E_SET_FC_AQ_FAIL_UPDATE = 4,
|
||||
I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
|
||||
};
|
||||
|
||||
enum i40e_vsi_type {
|
||||
I40E_VSI_MAIN = 0,
|
||||
I40E_VSI_VMDQ1 = 1,
|
||||
|
|
@ -134,162 +97,16 @@ enum i40e_queue_type {
|
|||
I40E_QUEUE_TYPE_UNKNOWN
|
||||
};
|
||||
|
||||
struct i40e_link_status {
|
||||
enum i40e_aq_phy_type phy_type;
|
||||
enum i40e_aq_link_speed link_speed;
|
||||
u8 link_info;
|
||||
u8 an_info;
|
||||
u8 req_fec_info;
|
||||
u8 fec_info;
|
||||
u8 ext_info;
|
||||
u8 loopback;
|
||||
/* is Link Status Event notification to SW enabled */
|
||||
bool lse_enable;
|
||||
u16 max_frame_size;
|
||||
bool crc_enable;
|
||||
u8 pacing;
|
||||
u8 requested_speeds;
|
||||
u8 module_type[3];
|
||||
/* 1st byte: module identifier */
|
||||
#define I40E_MODULE_TYPE_SFP 0x03
|
||||
#define I40E_MODULE_TYPE_QSFP 0x0D
|
||||
/* 2nd byte: ethernet compliance codes for 10/40G */
|
||||
#define I40E_MODULE_TYPE_40G_ACTIVE 0x01
|
||||
#define I40E_MODULE_TYPE_40G_LR4 0x02
|
||||
#define I40E_MODULE_TYPE_40G_SR4 0x04
|
||||
#define I40E_MODULE_TYPE_40G_CR4 0x08
|
||||
#define I40E_MODULE_TYPE_10G_BASE_SR 0x10
|
||||
#define I40E_MODULE_TYPE_10G_BASE_LR 0x20
|
||||
#define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
|
||||
#define I40E_MODULE_TYPE_10G_BASE_ER 0x80
|
||||
/* 3rd byte: ethernet compliance codes for 1G */
|
||||
#define I40E_MODULE_TYPE_1000BASE_SX 0x01
|
||||
#define I40E_MODULE_TYPE_1000BASE_LX 0x02
|
||||
#define I40E_MODULE_TYPE_1000BASE_CX 0x04
|
||||
#define I40E_MODULE_TYPE_1000BASE_T 0x08
|
||||
};
|
||||
|
||||
struct i40e_phy_info {
|
||||
struct i40e_link_status link_info;
|
||||
struct i40e_link_status link_info_old;
|
||||
bool get_link_info;
|
||||
enum i40e_media_type media_type;
|
||||
/* all the phy types the NVM is capable of */
|
||||
u64 phy_types;
|
||||
};
|
||||
|
||||
#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
|
||||
#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
|
||||
#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
|
||||
#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
|
||||
#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
|
||||
#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
|
||||
#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
|
||||
#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
|
||||
#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
|
||||
#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
|
||||
#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
|
||||
#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
|
||||
#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
|
||||
#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
|
||||
#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
|
||||
#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
|
||||
#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
|
||||
#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
|
||||
#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
|
||||
#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
|
||||
#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
|
||||
#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
|
||||
#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
|
||||
#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
|
||||
#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
|
||||
#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
|
||||
#define I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
|
||||
BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
|
||||
#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
|
||||
/* Defining the macro I40E_TYPE_OFFSET to implement a bit shift for some
|
||||
* PHY types. There is an unused bit (31) in the I40E_CAP_PHY_TYPE_* bit
|
||||
* fields but no corresponding gap in the i40e_aq_phy_type enumeration. So,
|
||||
* a shift is needed to adjust for this with values larger than 31. The
|
||||
* only affected values are I40E_PHY_TYPE_25GBASE_*.
|
||||
*/
|
||||
#define I40E_PHY_TYPE_OFFSET 1
|
||||
#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
|
||||
I40E_PHY_TYPE_OFFSET)
|
||||
#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
|
||||
I40E_PHY_TYPE_OFFSET)
|
||||
#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
|
||||
I40E_PHY_TYPE_OFFSET)
|
||||
#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
|
||||
I40E_PHY_TYPE_OFFSET)
|
||||
#define I40E_HW_CAP_MAX_GPIO 30
|
||||
#define I40E_HW_CAP_MAX_GPIO 30
|
||||
/* Capabilities of a PF or a VF or the whole device */
|
||||
struct i40e_hw_capabilities {
|
||||
u32 switch_mode;
|
||||
#define I40E_NVM_IMAGE_TYPE_EVB 0x0
|
||||
#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
|
||||
#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
|
||||
|
||||
u32 management_mode;
|
||||
u32 mng_protocols_over_mctp;
|
||||
#define I40E_MNG_PROTOCOL_PLDM 0x2
|
||||
#define I40E_MNG_PROTOCOL_OEM_COMMANDS 0x4
|
||||
#define I40E_MNG_PROTOCOL_NCSI 0x8
|
||||
u32 npar_enable;
|
||||
u32 os2bmc;
|
||||
u32 valid_functions;
|
||||
bool sr_iov_1_1;
|
||||
bool vmdq;
|
||||
bool evb_802_1_qbg; /* Edge Virtual Bridging */
|
||||
bool evb_802_1_qbh; /* Bridge Port Extension */
|
||||
bool dcb;
|
||||
bool fcoe;
|
||||
bool iscsi; /* Indicates iSCSI enabled */
|
||||
bool flex10_enable;
|
||||
bool flex10_capable;
|
||||
u32 flex10_mode;
|
||||
#define I40E_FLEX10_MODE_UNKNOWN 0x0
|
||||
#define I40E_FLEX10_MODE_DCC 0x1
|
||||
#define I40E_FLEX10_MODE_DCI 0x2
|
||||
|
||||
u32 flex10_status;
|
||||
#define I40E_FLEX10_STATUS_DCC_ERROR 0x1
|
||||
#define I40E_FLEX10_STATUS_VC_MODE 0x2
|
||||
|
||||
bool sec_rev_disabled;
|
||||
bool update_disabled;
|
||||
#define I40E_NVM_MGMT_SEC_REV_DISABLED 0x1
|
||||
#define I40E_NVM_MGMT_UPDATE_DISABLED 0x2
|
||||
|
||||
bool mgmt_cem;
|
||||
bool ieee_1588;
|
||||
bool iwarp;
|
||||
bool fd;
|
||||
u32 fd_filters_guaranteed;
|
||||
u32 fd_filters_best_effort;
|
||||
bool rss;
|
||||
u32 rss_table_size;
|
||||
u32 rss_table_entry_width;
|
||||
bool led[I40E_HW_CAP_MAX_GPIO];
|
||||
bool sdp[I40E_HW_CAP_MAX_GPIO];
|
||||
u32 nvm_image_type;
|
||||
u32 num_flow_director_filters;
|
||||
u32 num_vfs;
|
||||
u32 vf_base_id;
|
||||
u32 num_vsis;
|
||||
u32 num_rx_qp;
|
||||
u32 num_tx_qp;
|
||||
u32 base_queue;
|
||||
u32 num_msix_vectors;
|
||||
u32 num_msix_vectors_vf;
|
||||
u32 led_pin_num;
|
||||
u32 sdp_pin_num;
|
||||
u32 mdio_port_num;
|
||||
u32 mdio_port_mode;
|
||||
u8 rx_buf_chain_len;
|
||||
u32 enabled_tcmap;
|
||||
u32 maxtc;
|
||||
u64 wr_csr_prot;
|
||||
};
|
||||
|
||||
struct i40e_mac_info {
|
||||
|
|
@ -300,106 +117,6 @@ struct i40e_mac_info {
|
|||
u16 max_fcoeq;
|
||||
};
|
||||
|
||||
enum i40e_aq_resources_ids {
|
||||
I40E_NVM_RESOURCE_ID = 1
|
||||
};
|
||||
|
||||
enum i40e_aq_resource_access_type {
|
||||
I40E_RESOURCE_READ = 1,
|
||||
I40E_RESOURCE_WRITE
|
||||
};
|
||||
|
||||
struct i40e_nvm_info {
|
||||
u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
|
||||
u32 timeout; /* [ms] */
|
||||
u16 sr_size; /* Shadow RAM size in words */
|
||||
bool blank_nvm_mode; /* is NVM empty (no FW present)*/
|
||||
u16 version; /* NVM package version */
|
||||
u32 eetrack; /* NVM data version */
|
||||
u32 oem_ver; /* OEM version info */
|
||||
};
|
||||
|
||||
/* definitions used in NVM update support */
|
||||
|
||||
enum i40e_nvmupd_cmd {
|
||||
I40E_NVMUPD_INVALID,
|
||||
I40E_NVMUPD_READ_CON,
|
||||
I40E_NVMUPD_READ_SNT,
|
||||
I40E_NVMUPD_READ_LCB,
|
||||
I40E_NVMUPD_READ_SA,
|
||||
I40E_NVMUPD_WRITE_ERA,
|
||||
I40E_NVMUPD_WRITE_CON,
|
||||
I40E_NVMUPD_WRITE_SNT,
|
||||
I40E_NVMUPD_WRITE_LCB,
|
||||
I40E_NVMUPD_WRITE_SA,
|
||||
I40E_NVMUPD_CSUM_CON,
|
||||
I40E_NVMUPD_CSUM_SA,
|
||||
I40E_NVMUPD_CSUM_LCB,
|
||||
I40E_NVMUPD_STATUS,
|
||||
I40E_NVMUPD_EXEC_AQ,
|
||||
I40E_NVMUPD_GET_AQ_RESULT,
|
||||
I40E_NVMUPD_GET_AQ_EVENT,
|
||||
};
|
||||
|
||||
enum i40e_nvmupd_state {
|
||||
I40E_NVMUPD_STATE_INIT,
|
||||
I40E_NVMUPD_STATE_READING,
|
||||
I40E_NVMUPD_STATE_WRITING,
|
||||
I40E_NVMUPD_STATE_INIT_WAIT,
|
||||
I40E_NVMUPD_STATE_WRITE_WAIT,
|
||||
I40E_NVMUPD_STATE_ERROR
|
||||
};
|
||||
|
||||
/* nvm_access definition and its masks/shifts need to be accessible to
|
||||
* application, core driver, and shared code. Where is the right file?
|
||||
*/
|
||||
#define I40E_NVM_READ 0xB
|
||||
#define I40E_NVM_WRITE 0xC
|
||||
|
||||
#define I40E_NVM_MOD_PNT_MASK 0xFF
|
||||
|
||||
#define I40E_NVM_TRANS_SHIFT 8
|
||||
#define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
|
||||
#define I40E_NVM_PRESERVATION_FLAGS_SHIFT 12
|
||||
#define I40E_NVM_PRESERVATION_FLAGS_MASK \
|
||||
(0x3 << I40E_NVM_PRESERVATION_FLAGS_SHIFT)
|
||||
#define I40E_NVM_PRESERVATION_FLAGS_SELECTED 0x01
|
||||
#define I40E_NVM_PRESERVATION_FLAGS_ALL 0x02
|
||||
#define I40E_NVM_CON 0x0
|
||||
#define I40E_NVM_SNT 0x1
|
||||
#define I40E_NVM_LCB 0x2
|
||||
#define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
|
||||
#define I40E_NVM_ERA 0x4
|
||||
#define I40E_NVM_CSUM 0x8
|
||||
#define I40E_NVM_AQE 0xe
|
||||
#define I40E_NVM_EXEC 0xf
|
||||
|
||||
#define I40E_NVM_ADAPT_SHIFT 16
|
||||
#define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
|
||||
|
||||
#define I40E_NVMUPD_MAX_DATA 4096
|
||||
#define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
|
||||
|
||||
struct i40e_nvm_access {
|
||||
u32 command;
|
||||
u32 config;
|
||||
u32 offset; /* in bytes */
|
||||
u32 data_size; /* in bytes */
|
||||
u8 data[1];
|
||||
};
|
||||
|
||||
/* (Q)SFP module access definitions */
|
||||
#define I40E_I2C_EEPROM_DEV_ADDR 0xA0
|
||||
#define I40E_I2C_EEPROM_DEV_ADDR2 0xA2
|
||||
#define I40E_MODULE_TYPE_ADDR 0x00
|
||||
#define I40E_MODULE_REVISION_ADDR 0x01
|
||||
#define I40E_MODULE_SFF_8472_COMP 0x5E
|
||||
#define I40E_MODULE_SFF_8472_SWAP 0x5C
|
||||
#define I40E_MODULE_SFF_ADDR_MODE 0x04
|
||||
#define I40E_MODULE_TYPE_QSFP_PLUS 0x0D
|
||||
#define I40E_MODULE_TYPE_QSFP28 0x11
|
||||
#define I40E_MODULE_QSFP_MAX_LEN 640
|
||||
|
||||
/* PCI bus types */
|
||||
enum i40e_bus_type {
|
||||
i40e_bus_type_unknown = 0,
|
||||
|
|
@ -447,69 +164,16 @@ struct i40e_bus_info {
|
|||
u16 bus_id;
|
||||
};
|
||||
|
||||
/* Flow control (FC) parameters */
|
||||
struct i40e_fc_info {
|
||||
enum i40e_fc_mode current_mode; /* FC mode in effect */
|
||||
enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
|
||||
};
|
||||
|
||||
#define I40E_MAX_TRAFFIC_CLASS 8
|
||||
#define I40E_MAX_USER_PRIORITY 8
|
||||
#define I40E_DCBX_MAX_APPS 32
|
||||
#define I40E_LLDPDU_SIZE 1500
|
||||
|
||||
/* IEEE 802.1Qaz ETS Configuration data */
|
||||
struct i40e_ieee_ets_config {
|
||||
u8 willing;
|
||||
u8 cbs;
|
||||
u8 maxtcs;
|
||||
u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
|
||||
u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
|
||||
u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
|
||||
};
|
||||
|
||||
/* IEEE 802.1Qaz ETS Recommendation data */
|
||||
struct i40e_ieee_ets_recommend {
|
||||
u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
|
||||
u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
|
||||
u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
|
||||
};
|
||||
|
||||
/* IEEE 802.1Qaz PFC Configuration data */
|
||||
struct i40e_ieee_pfc_config {
|
||||
u8 willing;
|
||||
u8 mbc;
|
||||
u8 pfccap;
|
||||
u8 pfcenable;
|
||||
};
|
||||
|
||||
/* IEEE 802.1Qaz Application Priority data */
|
||||
struct i40e_ieee_app_priority_table {
|
||||
u8 priority;
|
||||
u8 selector;
|
||||
u16 protocolid;
|
||||
};
|
||||
|
||||
struct i40e_dcbx_config {
|
||||
u32 numapps;
|
||||
u32 tlv_status; /* CEE mode TLV status */
|
||||
struct i40e_ieee_ets_config etscfg;
|
||||
struct i40e_ieee_ets_recommend etsrec;
|
||||
struct i40e_ieee_pfc_config pfc;
|
||||
struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
|
||||
};
|
||||
|
||||
/* Port hardware description */
|
||||
struct i40e_hw {
|
||||
u8 __iomem *hw_addr;
|
||||
void *back;
|
||||
|
||||
/* subsystem structs */
|
||||
struct i40e_phy_info phy;
|
||||
struct i40e_mac_info mac;
|
||||
struct i40e_bus_info bus;
|
||||
struct i40e_nvm_info nvm;
|
||||
struct i40e_fc_info fc;
|
||||
|
||||
/* pci info */
|
||||
u16 device_id;
|
||||
|
|
@ -517,58 +181,13 @@ struct i40e_hw {
|
|||
u16 subsystem_device_id;
|
||||
u16 subsystem_vendor_id;
|
||||
u8 revision_id;
|
||||
u8 port;
|
||||
bool adapter_stopped;
|
||||
|
||||
/* capabilities for entire device and PCI func */
|
||||
struct i40e_hw_capabilities dev_caps;
|
||||
struct i40e_hw_capabilities func_caps;
|
||||
|
||||
/* Flow Director shared filter space */
|
||||
u16 fdir_shared_filter_count;
|
||||
|
||||
/* device profile info */
|
||||
u8 pf_id;
|
||||
u16 main_vsi_seid;
|
||||
|
||||
/* for multi-function MACs */
|
||||
u16 partition_id;
|
||||
u16 num_partitions;
|
||||
u16 num_ports;
|
||||
|
||||
/* Closest numa node to the device */
|
||||
u16 numa_node;
|
||||
|
||||
/* Admin Queue info */
|
||||
struct i40e_adminq_info aq;
|
||||
|
||||
/* state of nvm update process */
|
||||
enum i40e_nvmupd_state nvmupd_state;
|
||||
struct i40e_aq_desc nvm_wb_desc;
|
||||
struct i40e_aq_desc nvm_aq_event_desc;
|
||||
struct i40e_virt_mem nvm_buff;
|
||||
bool nvm_release_on_done;
|
||||
u16 nvm_wait_opcode;
|
||||
|
||||
/* HMC info */
|
||||
struct i40e_hmc_info hmc; /* HMC info struct */
|
||||
|
||||
/* LLDP/DCBX Status */
|
||||
u16 dcbx_status;
|
||||
|
||||
#define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
|
||||
#define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
|
||||
|
||||
/* DCBX info */
|
||||
struct i40e_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
|
||||
struct i40e_dcbx_config remote_dcbx_config; /* Peer Cfg */
|
||||
struct i40e_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
|
||||
|
||||
/* Used in set switch config AQ command */
|
||||
u16 switch_tag;
|
||||
u16 first_tag;
|
||||
u16 second_tag;
|
||||
|
||||
/* debug mask */
|
||||
u32 debug_mask;
|
||||
char err_str[16];
|
||||
|
|
@ -962,9 +581,6 @@ struct i40e_tx_context_desc {
|
|||
__le64 type_cmd_tso_mss;
|
||||
};
|
||||
|
||||
#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
|
||||
#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
|
||||
|
||||
#define I40E_TXD_CTX_QW1_CMD_SHIFT 4
|
||||
#define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
|
||||
|
||||
|
|
@ -1028,21 +644,6 @@ enum i40e_tx_ctx_desc_eipt_offload {
|
|||
|
||||
#define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
|
||||
#define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
|
||||
struct i40e_filter_program_desc {
|
||||
__le32 qindex_flex_ptype_vsi;
|
||||
__le32 rsvd;
|
||||
__le32 dtype_cmd_cntindex;
|
||||
__le32 fd_id;
|
||||
};
|
||||
#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
|
||||
#define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
|
||||
I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
|
||||
#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
|
||||
#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
|
||||
I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
|
||||
#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
|
||||
#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
|
||||
I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
|
||||
|
||||
/* Packet Classifier Types for filters */
|
||||
enum i40e_filter_pctype {
|
||||
|
|
@ -1076,58 +677,6 @@ enum i40e_filter_pctype {
|
|||
I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
|
||||
};
|
||||
|
||||
enum i40e_filter_program_desc_dest {
|
||||
I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
|
||||
I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
|
||||
I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
|
||||
};
|
||||
|
||||
enum i40e_filter_program_desc_fd_status {
|
||||
I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
|
||||
I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
|
||||
I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
|
||||
I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
|
||||
};
|
||||
|
||||
#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
|
||||
#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
|
||||
I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
|
||||
|
||||
#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
|
||||
#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
|
||||
I40E_TXD_FLTR_QW1_CMD_SHIFT)
|
||||
|
||||
#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
|
||||
#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
|
||||
|
||||
enum i40e_filter_program_desc_pcmd {
|
||||
I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
|
||||
I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
|
||||
};
|
||||
|
||||
#define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
|
||||
#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
|
||||
|
||||
#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
|
||||
#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
|
||||
|
||||
#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
|
||||
I40E_TXD_FLTR_QW1_CMD_SHIFT)
|
||||
#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
|
||||
I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
|
||||
|
||||
#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
|
||||
#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
|
||||
I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
|
||||
|
||||
enum i40e_filter_type {
|
||||
I40E_FLOW_DIRECTOR_FLTR = 0,
|
||||
I40E_PE_QUAD_HASH_FLTR = 1,
|
||||
I40E_ETHERTYPE_FLTR,
|
||||
I40E_FCOE_CTX_FLTR,
|
||||
I40E_MAC_VLAN_FLTR,
|
||||
I40E_HASH_FLTR
|
||||
};
|
||||
|
||||
struct i40e_vsi_context {
|
||||
u16 seid;
|
||||
|
|
@ -1167,330 +716,4 @@ struct i40e_eth_stats {
|
|||
u64 tx_discards; /* tdpc */
|
||||
u64 tx_errors; /* tepc */
|
||||
};
|
||||
|
||||
/* Statistics collected per VEB per TC */
|
||||
struct i40e_veb_tc_stats {
|
||||
u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
|
||||
u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
|
||||
u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
|
||||
u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
|
||||
};
|
||||
|
||||
/* Statistics collected by the MAC */
|
||||
struct i40e_hw_port_stats {
|
||||
/* eth stats collected by the port */
|
||||
struct i40e_eth_stats eth;
|
||||
|
||||
/* additional port specific stats */
|
||||
u64 tx_dropped_link_down; /* tdold */
|
||||
u64 crc_errors; /* crcerrs */
|
||||
u64 illegal_bytes; /* illerrc */
|
||||
u64 error_bytes; /* errbc */
|
||||
u64 mac_local_faults; /* mlfc */
|
||||
u64 mac_remote_faults; /* mrfc */
|
||||
u64 rx_length_errors; /* rlec */
|
||||
u64 link_xon_rx; /* lxonrxc */
|
||||
u64 link_xoff_rx; /* lxoffrxc */
|
||||
u64 priority_xon_rx[8]; /* pxonrxc[8] */
|
||||
u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
|
||||
u64 link_xon_tx; /* lxontxc */
|
||||
u64 link_xoff_tx; /* lxofftxc */
|
||||
u64 priority_xon_tx[8]; /* pxontxc[8] */
|
||||
u64 priority_xoff_tx[8]; /* pxofftxc[8] */
|
||||
u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
|
||||
u64 rx_size_64; /* prc64 */
|
||||
u64 rx_size_127; /* prc127 */
|
||||
u64 rx_size_255; /* prc255 */
|
||||
u64 rx_size_511; /* prc511 */
|
||||
u64 rx_size_1023; /* prc1023 */
|
||||
u64 rx_size_1522; /* prc1522 */
|
||||
u64 rx_size_big; /* prc9522 */
|
||||
u64 rx_undersize; /* ruc */
|
||||
u64 rx_fragments; /* rfc */
|
||||
u64 rx_oversize; /* roc */
|
||||
u64 rx_jabber; /* rjc */
|
||||
u64 tx_size_64; /* ptc64 */
|
||||
u64 tx_size_127; /* ptc127 */
|
||||
u64 tx_size_255; /* ptc255 */
|
||||
u64 tx_size_511; /* ptc511 */
|
||||
u64 tx_size_1023; /* ptc1023 */
|
||||
u64 tx_size_1522; /* ptc1522 */
|
||||
u64 tx_size_big; /* ptc9522 */
|
||||
u64 mac_short_packet_dropped; /* mspdc */
|
||||
u64 checksum_error; /* xec */
|
||||
/* flow director stats */
|
||||
u64 fd_atr_match;
|
||||
u64 fd_sb_match;
|
||||
u64 fd_atr_tunnel_match;
|
||||
u32 fd_atr_status;
|
||||
u32 fd_sb_status;
|
||||
/* EEE LPI */
|
||||
u32 tx_lpi_status;
|
||||
u32 rx_lpi_status;
|
||||
u64 tx_lpi_count; /* etlpic */
|
||||
u64 rx_lpi_count; /* erlpic */
|
||||
};
|
||||
|
||||
/* Checksum and Shadow RAM pointers */
|
||||
#define I40E_SR_NVM_CONTROL_WORD 0x00
|
||||
#define I40E_EMP_MODULE_PTR 0x0F
|
||||
#define I40E_SR_EMP_MODULE_PTR 0x48
|
||||
#define I40E_NVM_OEM_VER_OFF 0x83
|
||||
#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
|
||||
#define I40E_SR_NVM_WAKE_ON_LAN 0x19
|
||||
#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
|
||||
#define I40E_SR_NVM_EETRACK_LO 0x2D
|
||||
#define I40E_SR_NVM_EETRACK_HI 0x2E
|
||||
#define I40E_SR_VPD_PTR 0x2F
|
||||
#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
|
||||
#define I40E_SR_SW_CHECKSUM_WORD 0x3F
|
||||
|
||||
/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
|
||||
#define I40E_SR_VPD_MODULE_MAX_SIZE 1024
|
||||
#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
|
||||
#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
|
||||
#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
|
||||
#define I40E_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5)
|
||||
#define I40E_SR_NVM_MAP_STRUCTURE_TYPE BIT(12)
|
||||
#define I40E_PTR_TYPE BIT(15)
|
||||
|
||||
/* Shadow RAM related */
|
||||
#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
|
||||
#define I40E_SR_WORDS_IN_1KB 512
|
||||
/* Checksum should be calculated such that after adding all the words,
|
||||
* including the checksum word itself, the sum should be 0xBABA.
|
||||
*/
|
||||
#define I40E_SR_SW_CHECKSUM_BASE 0xBABA
|
||||
|
||||
#define I40E_SRRD_SRCTL_ATTEMPTS 100000
|
||||
|
||||
enum i40e_switch_element_types {
|
||||
I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
|
||||
I40E_SWITCH_ELEMENT_TYPE_PF = 2,
|
||||
I40E_SWITCH_ELEMENT_TYPE_VF = 3,
|
||||
I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
|
||||
I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
|
||||
I40E_SWITCH_ELEMENT_TYPE_PE = 16,
|
||||
I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
|
||||
I40E_SWITCH_ELEMENT_TYPE_PA = 18,
|
||||
I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
|
||||
};
|
||||
|
||||
/* Supported EtherType filters */
|
||||
enum i40e_ether_type_index {
|
||||
I40E_ETHER_TYPE_1588 = 0,
|
||||
I40E_ETHER_TYPE_FIP = 1,
|
||||
I40E_ETHER_TYPE_OUI_EXTENDED = 2,
|
||||
I40E_ETHER_TYPE_MAC_CONTROL = 3,
|
||||
I40E_ETHER_TYPE_LLDP = 4,
|
||||
I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
|
||||
I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
|
||||
I40E_ETHER_TYPE_QCN_CNM = 7,
|
||||
I40E_ETHER_TYPE_8021X = 8,
|
||||
I40E_ETHER_TYPE_ARP = 9,
|
||||
I40E_ETHER_TYPE_RSV1 = 10,
|
||||
I40E_ETHER_TYPE_RSV2 = 11,
|
||||
};
|
||||
|
||||
/* Filter context base size is 1K */
|
||||
#define I40E_HASH_FILTER_BASE_SIZE 1024
|
||||
/* Supported Hash filter values */
|
||||
enum i40e_hash_filter_size {
|
||||
I40E_HASH_FILTER_SIZE_1K = 0,
|
||||
I40E_HASH_FILTER_SIZE_2K = 1,
|
||||
I40E_HASH_FILTER_SIZE_4K = 2,
|
||||
I40E_HASH_FILTER_SIZE_8K = 3,
|
||||
I40E_HASH_FILTER_SIZE_16K = 4,
|
||||
I40E_HASH_FILTER_SIZE_32K = 5,
|
||||
I40E_HASH_FILTER_SIZE_64K = 6,
|
||||
I40E_HASH_FILTER_SIZE_128K = 7,
|
||||
I40E_HASH_FILTER_SIZE_256K = 8,
|
||||
I40E_HASH_FILTER_SIZE_512K = 9,
|
||||
I40E_HASH_FILTER_SIZE_1M = 10,
|
||||
};
|
||||
|
||||
/* DMA context base size is 0.5K */
|
||||
#define I40E_DMA_CNTX_BASE_SIZE 512
|
||||
/* Supported DMA context values */
|
||||
enum i40e_dma_cntx_size {
|
||||
I40E_DMA_CNTX_SIZE_512 = 0,
|
||||
I40E_DMA_CNTX_SIZE_1K = 1,
|
||||
I40E_DMA_CNTX_SIZE_2K = 2,
|
||||
I40E_DMA_CNTX_SIZE_4K = 3,
|
||||
I40E_DMA_CNTX_SIZE_8K = 4,
|
||||
I40E_DMA_CNTX_SIZE_16K = 5,
|
||||
I40E_DMA_CNTX_SIZE_32K = 6,
|
||||
I40E_DMA_CNTX_SIZE_64K = 7,
|
||||
I40E_DMA_CNTX_SIZE_128K = 8,
|
||||
I40E_DMA_CNTX_SIZE_256K = 9,
|
||||
};
|
||||
|
||||
/* Supported Hash look up table (LUT) sizes */
|
||||
enum i40e_hash_lut_size {
|
||||
I40E_HASH_LUT_SIZE_128 = 0,
|
||||
I40E_HASH_LUT_SIZE_512 = 1,
|
||||
};
|
||||
|
||||
/* Structure to hold a per PF filter control settings */
|
||||
struct i40e_filter_control_settings {
|
||||
/* number of PE Quad Hash filter buckets */
|
||||
enum i40e_hash_filter_size pe_filt_num;
|
||||
/* number of PE Quad Hash contexts */
|
||||
enum i40e_dma_cntx_size pe_cntx_num;
|
||||
/* number of FCoE filter buckets */
|
||||
enum i40e_hash_filter_size fcoe_filt_num;
|
||||
/* number of FCoE DDP contexts */
|
||||
enum i40e_dma_cntx_size fcoe_cntx_num;
|
||||
/* size of the Hash LUT */
|
||||
enum i40e_hash_lut_size hash_lut_size;
|
||||
/* enable FDIR filters for PF and its VFs */
|
||||
bool enable_fdir;
|
||||
/* enable Ethertype filters for PF and its VFs */
|
||||
bool enable_ethtype;
|
||||
/* enable MAC/VLAN filters for PF and its VFs */
|
||||
bool enable_macvlan;
|
||||
};
|
||||
|
||||
/* Structure to hold device level control filter counts */
|
||||
struct i40e_control_filter_stats {
|
||||
u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
|
||||
u16 etype_used; /* Used perfect EtherType filters */
|
||||
u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
|
||||
u16 etype_free; /* Un-used perfect EtherType filters */
|
||||
};
|
||||
|
||||
enum i40e_reset_type {
|
||||
I40E_RESET_POR = 0,
|
||||
I40E_RESET_CORER = 1,
|
||||
I40E_RESET_GLOBR = 2,
|
||||
I40E_RESET_EMPR = 3,
|
||||
};
|
||||
|
||||
/* IEEE 802.1AB LLDP Agent Variables from NVM */
|
||||
#define I40E_NVM_LLDP_CFG_PTR 0x06
|
||||
#define I40E_SR_LLDP_CFG_PTR 0x31
|
||||
|
||||
/* RSS Hash Table Size */
|
||||
#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
|
||||
|
||||
/* INPUT SET MASK for RSS, flow director and flexible payload */
|
||||
#define I40E_FD_INSET_L3_SRC_SHIFT 47
|
||||
#define I40E_FD_INSET_L3_SRC_WORD_MASK (0x3ULL << \
|
||||
I40E_FD_INSET_L3_SRC_SHIFT)
|
||||
#define I40E_FD_INSET_L3_DST_SHIFT 35
|
||||
#define I40E_FD_INSET_L3_DST_WORD_MASK (0x3ULL << \
|
||||
I40E_FD_INSET_L3_DST_SHIFT)
|
||||
#define I40E_FD_INSET_L4_SRC_SHIFT 34
|
||||
#define I40E_FD_INSET_L4_SRC_WORD_MASK (0x1ULL << \
|
||||
I40E_FD_INSET_L4_SRC_SHIFT)
|
||||
#define I40E_FD_INSET_L4_DST_SHIFT 33
|
||||
#define I40E_FD_INSET_L4_DST_WORD_MASK (0x1ULL << \
|
||||
I40E_FD_INSET_L4_DST_SHIFT)
|
||||
#define I40E_FD_INSET_VERIFY_TAG_SHIFT 31
|
||||
#define I40E_FD_INSET_VERIFY_TAG_WORD_MASK (0x3ULL << \
|
||||
I40E_FD_INSET_VERIFY_TAG_SHIFT)
|
||||
|
||||
#define I40E_FD_INSET_FLEX_WORD50_SHIFT 17
|
||||
#define I40E_FD_INSET_FLEX_WORD50_MASK (0x1ULL << \
|
||||
I40E_FD_INSET_FLEX_WORD50_SHIFT)
|
||||
#define I40E_FD_INSET_FLEX_WORD51_SHIFT 16
|
||||
#define I40E_FD_INSET_FLEX_WORD51_MASK (0x1ULL << \
|
||||
I40E_FD_INSET_FLEX_WORD51_SHIFT)
|
||||
#define I40E_FD_INSET_FLEX_WORD52_SHIFT 15
|
||||
#define I40E_FD_INSET_FLEX_WORD52_MASK (0x1ULL << \
|
||||
I40E_FD_INSET_FLEX_WORD52_SHIFT)
|
||||
#define I40E_FD_INSET_FLEX_WORD53_SHIFT 14
|
||||
#define I40E_FD_INSET_FLEX_WORD53_MASK (0x1ULL << \
|
||||
I40E_FD_INSET_FLEX_WORD53_SHIFT)
|
||||
#define I40E_FD_INSET_FLEX_WORD54_SHIFT 13
|
||||
#define I40E_FD_INSET_FLEX_WORD54_MASK (0x1ULL << \
|
||||
I40E_FD_INSET_FLEX_WORD54_SHIFT)
|
||||
#define I40E_FD_INSET_FLEX_WORD55_SHIFT 12
|
||||
#define I40E_FD_INSET_FLEX_WORD55_MASK (0x1ULL << \
|
||||
I40E_FD_INSET_FLEX_WORD55_SHIFT)
|
||||
#define I40E_FD_INSET_FLEX_WORD56_SHIFT 11
|
||||
#define I40E_FD_INSET_FLEX_WORD56_MASK (0x1ULL << \
|
||||
I40E_FD_INSET_FLEX_WORD56_SHIFT)
|
||||
#define I40E_FD_INSET_FLEX_WORD57_SHIFT 10
|
||||
#define I40E_FD_INSET_FLEX_WORD57_MASK (0x1ULL << \
|
||||
I40E_FD_INSET_FLEX_WORD57_SHIFT)
|
||||
|
||||
/* Version format for Dynamic Device Personalization(DDP) */
|
||||
struct i40e_ddp_version {
|
||||
u8 major;
|
||||
u8 minor;
|
||||
u8 update;
|
||||
u8 draft;
|
||||
};
|
||||
|
||||
#define I40E_DDP_NAME_SIZE 32
|
||||
|
||||
/* Package header */
|
||||
struct i40e_package_header {
|
||||
struct i40e_ddp_version version;
|
||||
u32 segment_count;
|
||||
u32 segment_offset[1];
|
||||
};
|
||||
|
||||
/* Generic segment header */
|
||||
struct i40e_generic_seg_header {
|
||||
#define SEGMENT_TYPE_METADATA 0x00000001
|
||||
#define SEGMENT_TYPE_NOTES 0x00000002
|
||||
#define SEGMENT_TYPE_I40E 0x00000011
|
||||
#define SEGMENT_TYPE_X722 0x00000012
|
||||
u32 type;
|
||||
struct i40e_ddp_version version;
|
||||
u32 size;
|
||||
char name[I40E_DDP_NAME_SIZE];
|
||||
};
|
||||
|
||||
struct i40e_metadata_segment {
|
||||
struct i40e_generic_seg_header header;
|
||||
struct i40e_ddp_version version;
|
||||
u32 track_id;
|
||||
char name[I40E_DDP_NAME_SIZE];
|
||||
};
|
||||
|
||||
struct i40e_device_id_entry {
|
||||
u32 vendor_dev_id;
|
||||
u32 sub_vendor_dev_id;
|
||||
};
|
||||
|
||||
struct i40e_profile_segment {
|
||||
struct i40e_generic_seg_header header;
|
||||
struct i40e_ddp_version version;
|
||||
char name[I40E_DDP_NAME_SIZE];
|
||||
u32 device_table_count;
|
||||
struct i40e_device_id_entry device_table[1];
|
||||
};
|
||||
|
||||
struct i40e_section_table {
|
||||
u32 section_count;
|
||||
u32 section_offset[1];
|
||||
};
|
||||
|
||||
struct i40e_profile_section_header {
|
||||
u16 tbl_size;
|
||||
u16 data_end;
|
||||
struct {
|
||||
#define SECTION_TYPE_INFO 0x00000010
|
||||
#define SECTION_TYPE_MMIO 0x00000800
|
||||
#define SECTION_TYPE_AQ 0x00000801
|
||||
#define SECTION_TYPE_NOTE 0x80000000
|
||||
#define SECTION_TYPE_NAME 0x80000001
|
||||
u32 type;
|
||||
u32 offset;
|
||||
u32 size;
|
||||
} section;
|
||||
};
|
||||
|
||||
struct i40e_profile_info {
|
||||
u32 track_id;
|
||||
struct i40e_ddp_version version;
|
||||
u8 op;
|
||||
#define I40E_DDP_ADD_TRACKID 0x01
|
||||
#define I40E_DDP_REMOVE_TRACKID 0x02
|
||||
u8 reserved[7];
|
||||
u8 name[I40E_DDP_NAME_SIZE];
|
||||
};
|
||||
#endif /* _I40E_TYPE_H_ */
|
||||
|
|
|
|||
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Reference in a new issue