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iommu/exynos: Turn on useful configuration options
This turns on FLPD_CACHE, ACGEN and SYSSEL. FLPD_CACHE is a cache of 1st level page table entries that contains the address of a 2nd level page table to reduce latency of page table walking. ACGEN is architectural clock gating that gates clocks by System MMU itself if it is not active. Note that ACGEN is different from clock gating by the CPU. ACGEN just gates clocks to the internal logic of System MMU while clock gating by the CPU gates clocks to the System MMU. SYSSEL selects System MMU version in some Exynos SoCs. Some Exynos SoCs have an option to select System MMU versions exclusively because the SoCs adopts new System MMU version experimentally. This also always selects LRU as TLB replacement policy. Selecting TLB replacement policy is deprecated from System MMU 3.2. TLB in System MMU 3.3 has single TLB replacement policy, LRU. The bit of MMU_CFG selecting TLB replacement policy is remained as reserved. QoS value of page table walking is set to 15 (highst value). System MMU 3.3 can inherit QoS value of page table walking from its master H/W's transaction. This new feature is enabled by default and QoS value written to MMU_CFG is ignored. This patch also adds simplifies the sysmmu version checking by introducing some macros. Signed-off-by: Cho KyongHo <pullip.cho@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
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6b21a5db36
commit
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1 changed files with 34 additions and 4 deletions
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@ -93,6 +93,13 @@ static u32 lv2ent_offset(sysmmu_iova_t iova)
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#define CTRL_BLOCK 0x7
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#define CTRL_DISABLE 0x0
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#define CFG_LRU 0x1
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#define CFG_QOS(n) ((n & 0xF) << 7)
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#define CFG_MASK 0x0150FFFF /* Selecting bit 0-15, 20, 22 and 24 */
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#define CFG_ACGEN (1 << 24) /* System MMU 3.3 only */
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#define CFG_SYSSEL (1 << 22) /* System MMU 3.2 only */
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#define CFG_FLPDCACHE (1 << 20) /* System MMU 3.2+ only */
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#define REG_MMU_CTRL 0x000
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#define REG_MMU_CFG 0x004
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#define REG_MMU_STATUS 0x008
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@ -109,6 +116,12 @@ static u32 lv2ent_offset(sysmmu_iova_t iova)
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#define REG_MMU_VERSION 0x034
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#define MMU_MAJ_VER(val) ((val) >> 7)
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#define MMU_MIN_VER(val) ((val) & 0x7F)
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#define MMU_RAW_VER(reg) (((reg) >> 21) & ((1 << 11) - 1)) /* 11 bits */
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#define MAKE_MMU_VER(maj, min) ((((maj) & 0xF) << 7) | ((min) & 0x7F))
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#define REG_PB0_SADDR 0x04C
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#define REG_PB0_EADDR 0x050
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#define REG_PB1_SADDR 0x054
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@ -219,6 +232,11 @@ static void sysmmu_unblock(void __iomem *sfrbase)
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__raw_writel(CTRL_ENABLE, sfrbase + REG_MMU_CTRL);
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}
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static unsigned int __raw_sysmmu_version(struct sysmmu_drvdata *data)
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{
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return MMU_RAW_VER(__raw_readl(data->sfrbase + REG_MMU_VERSION));
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}
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static bool sysmmu_block(void __iomem *sfrbase)
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{
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int i = 120;
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@ -374,7 +392,21 @@ static bool __sysmmu_disable(struct sysmmu_drvdata *data)
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static void __sysmmu_init_config(struct sysmmu_drvdata *data)
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{
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unsigned int cfg = 0;
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unsigned int cfg = CFG_LRU | CFG_QOS(15);
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unsigned int ver;
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ver = __raw_sysmmu_version(data);
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if (MMU_MAJ_VER(ver) == 3) {
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if (MMU_MIN_VER(ver) >= 2) {
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cfg |= CFG_FLPDCACHE;
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if (MMU_MIN_VER(ver) == 3) {
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cfg |= CFG_ACGEN;
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cfg &= ~CFG_LRU;
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} else {
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cfg |= CFG_SYSSEL;
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}
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}
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}
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__raw_writel(cfg, data->sfrbase + REG_MMU_CFG);
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}
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@ -494,13 +526,11 @@ static void sysmmu_tlb_invalidate_entry(struct device *dev, sysmmu_iova_t iova,
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spin_lock_irqsave(&data->lock, flags);
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if (is_sysmmu_active(data)) {
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unsigned int maj;
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unsigned int num_inv = 1;
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if (!IS_ERR(data->clk_master))
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clk_enable(data->clk_master);
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maj = __raw_readl(data->sfrbase + REG_MMU_VERSION);
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/*
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* L2TLB invalidation required
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* 4KB page: 1 invalidation
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@ -511,7 +541,7 @@ static void sysmmu_tlb_invalidate_entry(struct device *dev, sysmmu_iova_t iova,
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* 1MB page can be cached in one of all sets.
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* 64KB page can be one of 16 consecutive sets.
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*/
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if ((maj >> 28) == 2) /* major version number */
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if (MMU_MAJ_VER(__raw_sysmmu_version(data)) == 2)
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num_inv = min_t(unsigned int, size / PAGE_SIZE, 64);
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if (sysmmu_block(data->sfrbase)) {
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