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spi: sirf: provide a shortcut for spi command-data mode
there are many SPI clients which use the following protocal: step 1: send command bytes to clients(rx buffer is empty) step 2: send data bytes to clients or receive data bytes from clients. SiRFprimaII provides a shortcut for this kind of SPI transfer. when tx buf is less or equal than 4 bytes and rx buf is null in a transfer, we think it as 'command' data and use hardware command register for the transfer. here we can save some CPU loading than doing both tx and rx for a normal transfer. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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1 changed files with 50 additions and 0 deletions
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@ -131,6 +131,8 @@
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#define IS_DMA_VALID(x) (x && ALIGNED(x->tx_buf) && ALIGNED(x->rx_buf) && \
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ALIGNED(x->len) && (x->len < 2 * PAGE_SIZE))
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#define SIRFSOC_MAX_CMD_BYTES 4
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struct sirfsoc_spi {
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struct spi_bitbang bitbang;
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struct completion rx_done;
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@ -161,6 +163,12 @@ struct sirfsoc_spi {
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void *dummypage;
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int word_width; /* in bytes */
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/*
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* if tx size is not more than 4 and rx size is NULL, use
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* command model
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*/
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bool tx_by_cmd;
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int chipselect[0];
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};
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@ -259,6 +267,12 @@ static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
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writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS);
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if (sspi->tx_by_cmd && (spi_stat & SIRFSOC_SPI_FRM_END)) {
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complete(&sspi->tx_done);
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writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
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return IRQ_HANDLED;
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}
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/* Error Conditions */
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if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
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spi_stat & SIRFSOC_SPI_TX_UFLOW) {
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@ -309,6 +323,34 @@ static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
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writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
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/*
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* fill tx_buf into command register and wait for its completion
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*/
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if (sspi->tx_by_cmd) {
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u32 cmd;
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memcpy(&cmd, sspi->tx, t->len);
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if (sspi->word_width == 1 && !(spi->mode & SPI_LSB_FIRST))
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cmd = cpu_to_be32(cmd) >>
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((SIRFSOC_MAX_CMD_BYTES - t->len) * 8);
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if (sspi->word_width == 2 && t->len == 4 &&
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(!(spi->mode & SPI_LSB_FIRST)))
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cmd = ((cmd & 0xffff) << 16) | (cmd >> 16);
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writel(cmd, sspi->base + SIRFSOC_SPI_CMD);
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writel(SIRFSOC_SPI_FRM_END_INT_EN,
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sspi->base + SIRFSOC_SPI_INT_EN);
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writel(SIRFSOC_SPI_CMD_TX_EN,
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sspi->base + SIRFSOC_SPI_TX_RX_EN);
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if (wait_for_completion_timeout(&sspi->tx_done, timeout) == 0) {
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dev_err(&spi->dev, "transfer timeout\n");
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return 0;
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}
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return t->len;
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}
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if (sspi->left_tx_word == 1) {
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writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
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SIRFSOC_SPI_ENA_AUTO_CLR,
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@ -509,6 +551,14 @@ spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
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writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL);
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writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL);
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if (t && t->tx_buf && !t->rx_buf && (t->len <= SIRFSOC_MAX_CMD_BYTES)) {
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regval |= (SIRFSOC_SPI_CMD_BYTE_NUM((t->len - 1)) |
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SIRFSOC_SPI_CMD_MODE);
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sspi->tx_by_cmd = true;
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} else {
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regval &= ~SIRFSOC_SPI_CMD_MODE;
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sspi->tx_by_cmd = false;
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}
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writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
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if (IS_DMA_VALID(t)) {
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