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i2c: exynos5: Describe the hardware variant for readability
The driver supports multiple hardware variants of Exynos I2C controller which differ in FIFO depth, handling of interrupts and bus recovery in HSI2C_MASTER_ST_LOSE state. The difference in variant was a single bit set for Exynos7 variants and implicit lack of this bit for other variants. Make each variant explicit which also fixes the GCC warning about documentation: drivers/i2c/busses/i2c-exynos5.c:223: warning: Function parameter or member 'hw' not described in 'exynos_hsi2c_variant' No change in functionality. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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1 changed files with 14 additions and 8 deletions
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@ -176,7 +176,10 @@
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#define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(100))
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#define HSI2C_EXYNOS7 BIT(0)
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enum i2c_type_exynos {
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I2C_TYPE_EXYNOS5,
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I2C_TYPE_EXYNOS7,
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};
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struct exynos5_i2c {
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struct i2c_adapter adap;
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@ -212,27 +215,30 @@ struct exynos5_i2c {
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/**
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* struct exynos_hsi2c_variant - platform specific HSI2C driver data
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* @fifo_depth: the fifo depth supported by the HSI2C module
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* @hw: the hardware variant of Exynos I2C controller
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*
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* Specifies platform specific configuration of HSI2C module.
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* Note: A structure for driver specific platform data is used for future
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* expansion of its usage.
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*/
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struct exynos_hsi2c_variant {
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unsigned int fifo_depth;
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unsigned int hw;
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unsigned int fifo_depth;
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enum i2c_type_exynos hw;
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};
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static const struct exynos_hsi2c_variant exynos5250_hsi2c_data = {
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.fifo_depth = 64,
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.hw = I2C_TYPE_EXYNOS5,
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};
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static const struct exynos_hsi2c_variant exynos5260_hsi2c_data = {
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.fifo_depth = 16,
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.hw = I2C_TYPE_EXYNOS5,
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};
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static const struct exynos_hsi2c_variant exynos7_hsi2c_data = {
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.fifo_depth = 16,
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.hw = HSI2C_EXYNOS7,
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.hw = I2C_TYPE_EXYNOS7,
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};
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static const struct of_device_id exynos5_i2c_match[] = {
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@ -300,7 +306,7 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
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*/
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t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
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temp = clkin / op_clk - 8 - t_ftl_cycle;
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if (i2c->variant->hw != HSI2C_EXYNOS7)
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if (i2c->variant->hw != I2C_TYPE_EXYNOS7)
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temp -= t_ftl_cycle;
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div = temp / 512;
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clk_cycle = temp / (div + 1) - 2;
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@ -424,7 +430,7 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
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writel(int_status, i2c->regs + HSI2C_INT_STATUS);
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/* handle interrupt related to the transfer status */
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if (i2c->variant->hw == HSI2C_EXYNOS7) {
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if (i2c->variant->hw == I2C_TYPE_EXYNOS7) {
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if (int_status & HSI2C_INT_TRANS_DONE) {
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i2c->trans_done = 1;
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i2c->state = 0;
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@ -571,7 +577,7 @@ static void exynos5_i2c_bus_check(struct exynos5_i2c *i2c)
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{
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unsigned long timeout;
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if (i2c->variant->hw != HSI2C_EXYNOS7)
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if (i2c->variant->hw != I2C_TYPE_EXYNOS7)
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return;
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/*
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@ -612,7 +618,7 @@ static void exynos5_i2c_message_start(struct exynos5_i2c *i2c, int stop)
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unsigned long flags;
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unsigned short trig_lvl;
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if (i2c->variant->hw == HSI2C_EXYNOS7)
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if (i2c->variant->hw == I2C_TYPE_EXYNOS7)
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int_en |= HSI2C_INT_I2C_TRANS;
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else
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int_en |= HSI2C_INT_I2C;
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