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mtd: m25p80: Micron SPI uses Macronix-style 4-byte addressing
For SPI NOR flash that are larger than 128Mbit (16MiB), we need 4 bytes of address space to reach the entire flash; however, the original SPI flash protocol used only 3 bytes for the address. So far, the practice for handling this has been either to use new command opcodes that are defined to use 4 bytes for their address, or to use special mode-switching command to configure all traditionally-3-byte-address commands to take 4 bytes instead. Macronix and Spansion developed two incompatible methods for entering/exiting "4-byte address mode." Micron flash uses the Macronix method (OPCODE_{EN4B,EX4B}), not the Spansion method. This patch solves addressing issues on Micron n25q256a and provides the ability to support other future Micron SPI flash >16MiB. Quoting a Micron representative: "Majority of our NOR that needs 4-byte addressing (256Mb or 32MB and higher) enter and exit 4byte through B7h and E9h commands. The N25Q256A7xxx and N25Q512A7xxx parts do not support 4-byte addressing mode via B7h or E9h command." They further clarified that those that don't support the enter/exit opcodes (B7h/E9h) are manufactured specifically to come up by default in 4-byte mode. We don't need to treat those parts any diffently, as they will discard the EN4B opcode as a no-op. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -169,6 +169,7 @@ static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
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{
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switch (JEDEC_MFR(jedec_id)) {
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case CFI_MFR_MACRONIX:
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case CFI_MFR_ST: /* Micron, actually */
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case 0xEF /* winbond */:
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flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
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return spi_write(flash->spi, flash->command, 1);
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