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bnx2x: Add timestamping and PTP hardware clock support
This adds a PHC to the bnx2x driver. Driver supports timestamping send/receive PTP packets, as well as adjusting the on-chip clock. The driver has been tested with linuxptp project. Signed-off-by: Michal Kalderon <Michal.Kalderon@qlogic.com> Signed-off-by: Yuval Mintz <Yuval.Mintz@qlogic.com> Signed-off-by: Ariel Elior <Ariel.Elior@qlogic.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
e42780b66a
commit
eeed018cbf
8 changed files with 984 additions and 13 deletions
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@ -20,6 +20,10 @@
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#include <linux/types.h>
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#include <linux/pci_regs.h>
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#include <linux/ptp_clock_kernel.h>
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#include <linux/net_tstamp.h>
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#include <linux/clocksource.h>
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/* compilation time flags */
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/* define this to make the driver freeze on error to allow getting debug info
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@ -70,6 +74,7 @@ enum bnx2x_int_mode {
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#define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
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#define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
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#define BNX2X_MSG_IOV 0x0800000
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#define BNX2X_MSG_PTP 0x1000000
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#define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
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#define BNX2X_MSG_ETHTOOL 0x4000000
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#define BNX2X_MSG_DCB 0x8000000
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@ -1591,6 +1596,8 @@ struct bnx2x {
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#define BC_SUPPORTS_RMMOD_CMD (1 << 24)
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#define HAS_PHYS_PORT_ID (1 << 25)
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#define AER_ENABLED (1 << 26)
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#define PTP_SUPPORTED (1 << 27)
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#define TX_TIMESTAMPING_EN (1 << 28)
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#define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG)
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@ -1933,6 +1940,19 @@ struct bnx2x {
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u8 phys_port_id[ETH_ALEN];
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/* PTP related context */
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struct ptp_clock *ptp_clock;
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struct ptp_clock_info ptp_clock_info;
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struct work_struct ptp_task;
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struct cyclecounter cyclecounter;
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struct timecounter timecounter;
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bool timecounter_init_done;
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struct sk_buff *ptp_tx_skb;
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unsigned long ptp_tx_start;
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bool hwtstamp_ioctl_called;
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u16 tx_type;
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u16 rx_filter;
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struct bnx2x_link_report_data vf_link_vars;
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};
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@ -2559,4 +2579,11 @@ void bnx2x_update_mng_version(struct bnx2x *bp);
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#define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX))
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void bnx2x_init_ptp(struct bnx2x *bp);
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int bnx2x_configure_ptp_filters(struct bnx2x *bp);
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void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb);
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#define BNX2X_MAX_PHC_DRIFT 31000000
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#define BNX2X_PTP_TX_TIMEOUT
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#endif /* bnx2x.h */
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@ -1067,6 +1067,11 @@ static int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
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skb_record_rx_queue(skb, fp->rx_queue);
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/* Check if this packet was timestamped */
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if (unlikely(le16_to_cpu(cqe->fast_path_cqe.type_error_flags) &
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(1 << ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT)))
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bnx2x_set_rx_ts(bp, skb);
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if (le16_to_cpu(cqe_fp->pars_flags.flags) &
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PARSING_FLAGS_VLAN)
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__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
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@ -2808,7 +2813,11 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
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/* Initialize Rx filter. */
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bnx2x_set_rx_mode_inner(bp);
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/* Start the Tx */
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if (bp->flags & PTP_SUPPORTED) {
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bnx2x_init_ptp(bp);
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bnx2x_configure_ptp_filters(bp);
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}
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/* Start Tx */
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switch (load_mode) {
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case LOAD_NORMAL:
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/* Tx queue should be only re-enabled */
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@ -3833,6 +3842,20 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
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tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
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if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
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if (!(bp->flags & TX_TIMESTAMPING_EN)) {
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BNX2X_ERR("Tx timestamping was not enabled, this packet will not be timestamped\n");
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} else if (bp->ptp_tx_skb) {
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BNX2X_ERR("The device supports only a single outstanding packet to timestamp, this packet will not be timestamped\n");
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} else {
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skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
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/* schedule check for Tx timestamp */
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bp->ptp_tx_skb = skb_get(skb);
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bp->ptp_tx_start = jiffies;
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schedule_work(&bp->ptp_task);
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}
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}
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/* header nbd: indirectly zero other flags! */
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tx_start_bd->general_data = 1 << ETH_TX_START_BD_HDR_NBDS_SHIFT;
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@ -3481,6 +3481,46 @@ static int bnx2x_set_channels(struct net_device *dev,
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return bnx2x_nic_load(bp, LOAD_NORMAL);
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}
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static int bnx2x_get_ts_info(struct net_device *dev,
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struct ethtool_ts_info *info)
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{
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struct bnx2x *bp = netdev_priv(dev);
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if (bp->flags & PTP_SUPPORTED) {
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info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
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SOF_TIMESTAMPING_RX_SOFTWARE |
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SOF_TIMESTAMPING_SOFTWARE |
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SOF_TIMESTAMPING_TX_HARDWARE |
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SOF_TIMESTAMPING_RX_HARDWARE |
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SOF_TIMESTAMPING_RAW_HARDWARE;
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if (bp->ptp_clock)
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info->phc_index = ptp_clock_index(bp->ptp_clock);
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else
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info->phc_index = -1;
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info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
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(1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
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(1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
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(1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
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(1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
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(1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
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(1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
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(1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
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(1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
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(1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
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(1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
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(1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
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(1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ);
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info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
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return 0;
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}
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return ethtool_op_get_ts_info(dev, info);
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}
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static const struct ethtool_ops bnx2x_ethtool_ops = {
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.get_settings = bnx2x_get_settings,
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.set_settings = bnx2x_set_settings,
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@ -3522,7 +3562,7 @@ static const struct ethtool_ops bnx2x_ethtool_ops = {
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.get_module_eeprom = bnx2x_get_module_eeprom,
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.get_eee = bnx2x_get_eee,
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.set_eee = bnx2x_set_eee,
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.get_ts_info = ethtool_op_get_ts_info,
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.get_ts_info = bnx2x_get_ts_info,
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};
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static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
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@ -3547,7 +3547,9 @@ struct client_init_rx_data {
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__le16 rx_cos_mask;
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__le16 silent_vlan_value;
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__le16 silent_vlan_mask;
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__le32 reserved6[2];
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u8 handle_ptp_pkts_flg;
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u8 reserved6[3];
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__le32 reserved7;
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};
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/*
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@ -3616,7 +3618,9 @@ struct client_update_ramrod_data {
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u8 refuse_outband_vlan_change_flg;
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u8 tx_switching_flg;
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u8 tx_switching_change_flg;
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__le32 reserved1;
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u8 handle_ptp_pkts_flg;
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u8 handle_ptp_pkts_change_flg;
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__le16 reserved1;
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__le32 echo;
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};
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@ -3850,8 +3854,10 @@ struct eth_fast_path_rx_cqe {
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#define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
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#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
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#define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
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#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
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#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
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#define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1<<6)
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#define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6
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#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1<<7)
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#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7
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u8 status_flags;
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#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
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#define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
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union protocol_common_specific_data data;
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};
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/* The data for the Set Timesync Ramrod */
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struct set_timesync_ramrod_data {
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u8 drift_adjust_cmd;
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u8 offset_cmd;
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u8 add_sub_drift_adjust_value;
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u8 drift_adjust_value;
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u32 drift_adjust_period;
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struct regpair offset_delta;
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};
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/*
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* The send queue element
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*/
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struct regpair reserved;
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};
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/* Add or Subtract Value for Set Timesync Ramrod */
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enum ts_add_sub_value {
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TS_SUB_VALUE,
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TS_ADD_VALUE,
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MAX_TS_ADD_SUB_VALUE
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};
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/* Drift-Adjust Commands for Set Timesync Ramrod */
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enum ts_drift_adjust_cmd {
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TS_DRIFT_ADJUST_KEEP,
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TS_DRIFT_ADJUST_SET,
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TS_DRIFT_ADJUST_RESET,
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MAX_TS_DRIFT_ADJUST_CMD
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};
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/* Offset Commands for Set Timesync Ramrod */
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enum ts_offset_cmd {
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TS_OFFSET_KEEP,
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TS_OFFSET_INC,
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TS_OFFSET_DEC,
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MAX_TS_OFFSET_CMD
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};
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/* Tunnel Mode */
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enum tunnel_mode {
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TUNN_MODE_NONE,
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@ -63,7 +63,6 @@
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#include "bnx2x_vfpf.h"
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#include "bnx2x_dcb.h"
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#include "bnx2x_sp.h"
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#include <linux/firmware.h>
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#include "bnx2x_fw_file_hdr.h"
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/* FW files */
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@ -290,6 +289,8 @@ static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
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* General service functions
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****************************************************************************/
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static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
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static void __storm_memset_dma_mapping(struct bnx2x *bp,
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u32 addr, dma_addr_t mapping)
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{
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@ -523,6 +524,7 @@ int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
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* as long as this code is called both from syscall context and
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* from ndo_set_rx_mode() flow that may be called from BH.
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*/
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spin_lock_bh(&bp->dmae_lock);
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/* reset completion */
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}
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unlock:
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spin_unlock_bh(&bp->dmae_lock);
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return rc;
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}
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@ -5452,6 +5456,14 @@ static void bnx2x_eq_int(struct bnx2x *bp)
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break;
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goto next_spqe;
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case EVENT_RING_OPCODE_SET_TIMESYNC:
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DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
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"got set_timesync ramrod completion\n");
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if (f_obj->complete_cmd(bp, f_obj,
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BNX2X_F_CMD_SET_TIMESYNC))
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break;
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goto next_spqe;
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}
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switch (opcode | bp->state) {
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@ -9033,6 +9045,48 @@ static int bnx2x_func_wait_started(struct bnx2x *bp)
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return 0;
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}
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static void bnx2x_disable_ptp(struct bnx2x *bp)
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{
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int port = BP_PORT(bp);
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/* Disable sending PTP packets to host */
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REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
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NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
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/* Reset PTP event detection rules */
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REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
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NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
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REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
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NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
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REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
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NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
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REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
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NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
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/* Disable the PTP feature */
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REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
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NIG_REG_P0_PTP_EN, 0x0);
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}
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/* Called during unload, to stop PTP-related stuff */
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void bnx2x_stop_ptp(struct bnx2x *bp)
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{
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/* Cancel PTP work queue. Should be done after the Tx queues are
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* drained to prevent additional scheduling.
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*/
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cancel_work_sync(&bp->ptp_task);
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if (bp->ptp_tx_skb) {
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dev_kfree_skb_any(bp->ptp_tx_skb);
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bp->ptp_tx_skb = NULL;
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}
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/* Disable PTP in HW */
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bnx2x_disable_ptp(bp);
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DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
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}
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void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
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{
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int port = BP_PORT(bp);
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@ -9151,6 +9205,13 @@ void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
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#endif
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}
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/* stop_ptp should be after the Tx queues are drained to prevent
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* scheduling to the cancelled PTP work queue. It should also be after
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* function stop ramrod is sent, since as part of this ramrod FW access
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* PTP registers.
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*/
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bnx2x_stop_ptp(bp);
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/* Disable HW interrupts, NAPI */
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bnx2x_netif_stop(bp, 1);
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/* Delete all NAPI objects */
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@ -12023,6 +12084,9 @@ static int bnx2x_init_bp(struct bnx2x *bp)
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bp->dump_preset_idx = 1;
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if (CHIP_IS_E3B0(bp))
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bp->flags |= PTP_SUPPORTED;
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return rc;
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}
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@ -12355,13 +12419,17 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
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struct bnx2x *bp = netdev_priv(dev);
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struct mii_ioctl_data *mdio = if_mii(ifr);
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DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
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mdio->phy_id, mdio->reg_num, mdio->val_in);
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if (!netif_running(dev))
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return -EAGAIN;
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return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
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switch (cmd) {
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case SIOCSHWTSTAMP:
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return bnx2x_hwtstamp_ioctl(bp, ifr);
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default:
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DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
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mdio->phy_id, mdio->reg_num, mdio->val_in);
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return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
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}
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}
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#ifdef CONFIG_NET_POLL_CONTROLLER
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@ -13005,6 +13073,191 @@ static int set_is_vf(int chip_id)
|
|||
}
|
||||
}
|
||||
|
||||
/* nig_tsgen registers relative address */
|
||||
#define tsgen_ctrl 0x0
|
||||
#define tsgen_freecount 0x10
|
||||
#define tsgen_synctime_t0 0x20
|
||||
#define tsgen_offset_t0 0x28
|
||||
#define tsgen_drift_t0 0x30
|
||||
#define tsgen_synctime_t1 0x58
|
||||
#define tsgen_offset_t1 0x60
|
||||
#define tsgen_drift_t1 0x68
|
||||
|
||||
/* FW workaround for setting drift */
|
||||
static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
|
||||
int best_val, int best_period)
|
||||
{
|
||||
struct bnx2x_func_state_params func_params = {NULL};
|
||||
struct bnx2x_func_set_timesync_params *set_timesync_params =
|
||||
&func_params.params.set_timesync;
|
||||
|
||||
/* Prepare parameters for function state transitions */
|
||||
__set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
|
||||
__set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
|
||||
|
||||
func_params.f_obj = &bp->func_obj;
|
||||
func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
|
||||
|
||||
/* Function parameters */
|
||||
set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
|
||||
set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
|
||||
set_timesync_params->add_sub_drift_adjust_value =
|
||||
drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
|
||||
set_timesync_params->drift_adjust_value = best_val;
|
||||
set_timesync_params->drift_adjust_period = best_period;
|
||||
|
||||
return bnx2x_func_state_change(bp, &func_params);
|
||||
}
|
||||
|
||||
static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
|
||||
{
|
||||
struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
|
||||
int rc;
|
||||
int drift_dir = 1;
|
||||
int val, period, period1, period2, dif, dif1, dif2;
|
||||
int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
|
||||
|
||||
DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
|
||||
|
||||
if (!netif_running(bp->dev)) {
|
||||
DP(BNX2X_MSG_PTP,
|
||||
"PTP adjfreq called while the interface is down\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
if (ppb < 0) {
|
||||
ppb = -ppb;
|
||||
drift_dir = 0;
|
||||
}
|
||||
|
||||
if (ppb == 0) {
|
||||
best_val = 1;
|
||||
best_period = 0x1FFFFFF;
|
||||
} else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
|
||||
best_val = 31;
|
||||
best_period = 1;
|
||||
} else {
|
||||
/* Changed not to allow val = 8, 16, 24 as these values
|
||||
* are not supported in workaround.
|
||||
*/
|
||||
for (val = 0; val <= 31; val++) {
|
||||
if ((val & 0x7) == 0)
|
||||
continue;
|
||||
period1 = val * 1000000 / ppb;
|
||||
period2 = period1 + 1;
|
||||
if (period1 != 0)
|
||||
dif1 = ppb - (val * 1000000 / period1);
|
||||
else
|
||||
dif1 = BNX2X_MAX_PHC_DRIFT;
|
||||
if (dif1 < 0)
|
||||
dif1 = -dif1;
|
||||
dif2 = ppb - (val * 1000000 / period2);
|
||||
if (dif2 < 0)
|
||||
dif2 = -dif2;
|
||||
dif = (dif1 < dif2) ? dif1 : dif2;
|
||||
period = (dif1 < dif2) ? period1 : period2;
|
||||
if (dif < best_dif) {
|
||||
best_dif = dif;
|
||||
best_val = val;
|
||||
best_period = period;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
|
||||
best_period);
|
||||
if (rc) {
|
||||
BNX2X_ERR("Failed to set drift\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
DP(BNX2X_MSG_PTP, "Configrued val = %d, period = %d\n", best_val,
|
||||
best_period);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
|
||||
{
|
||||
struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
|
||||
u64 now;
|
||||
|
||||
DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
|
||||
|
||||
now = timecounter_read(&bp->timecounter);
|
||||
now += delta;
|
||||
/* Re-init the timecounter */
|
||||
timecounter_init(&bp->timecounter, &bp->cyclecounter, now);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
|
||||
{
|
||||
struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
|
||||
u64 ns;
|
||||
u32 remainder;
|
||||
|
||||
ns = timecounter_read(&bp->timecounter);
|
||||
|
||||
DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
|
||||
|
||||
ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
|
||||
ts->tv_nsec = remainder;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
|
||||
const struct timespec *ts)
|
||||
{
|
||||
struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
|
||||
u64 ns;
|
||||
|
||||
ns = ts->tv_sec * 1000000000ULL;
|
||||
ns += ts->tv_nsec;
|
||||
|
||||
DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
|
||||
|
||||
/* Re-init the timecounter */
|
||||
timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Enable (or disable) ancillary features of the phc subsystem */
|
||||
static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
|
||||
struct ptp_clock_request *rq, int on)
|
||||
{
|
||||
struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
|
||||
|
||||
BNX2X_ERR("PHC ancillary features are not supported\n");
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
void bnx2x_register_phc(struct bnx2x *bp)
|
||||
{
|
||||
/* Fill the ptp_clock_info struct and register PTP clock*/
|
||||
bp->ptp_clock_info.owner = THIS_MODULE;
|
||||
snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
|
||||
bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
|
||||
bp->ptp_clock_info.n_alarm = 0;
|
||||
bp->ptp_clock_info.n_ext_ts = 0;
|
||||
bp->ptp_clock_info.n_per_out = 0;
|
||||
bp->ptp_clock_info.pps = 0;
|
||||
bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
|
||||
bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
|
||||
bp->ptp_clock_info.gettime = bnx2x_ptp_gettime;
|
||||
bp->ptp_clock_info.settime = bnx2x_ptp_settime;
|
||||
bp->ptp_clock_info.enable = bnx2x_ptp_enable;
|
||||
|
||||
bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
|
||||
if (IS_ERR(bp->ptp_clock)) {
|
||||
bp->ptp_clock = NULL;
|
||||
BNX2X_ERR("PTP clock registeration failed\n");
|
||||
}
|
||||
}
|
||||
|
||||
static int bnx2x_init_one(struct pci_dev *pdev,
|
||||
const struct pci_device_id *ent)
|
||||
{
|
||||
|
@ -13176,6 +13429,8 @@ static int bnx2x_init_one(struct pci_dev *pdev,
|
|||
"Unknown",
|
||||
dev->base_addr, bp->pdev->irq, dev->dev_addr);
|
||||
|
||||
bnx2x_register_phc(bp);
|
||||
|
||||
return 0;
|
||||
|
||||
init_one_exit:
|
||||
|
@ -13202,6 +13457,11 @@ static void __bnx2x_remove(struct pci_dev *pdev,
|
|||
struct bnx2x *bp,
|
||||
bool remove_netdev)
|
||||
{
|
||||
if (bp->ptp_clock) {
|
||||
ptp_clock_unregister(bp->ptp_clock);
|
||||
bp->ptp_clock = NULL;
|
||||
}
|
||||
|
||||
/* Delete storage MAC address */
|
||||
if (!NO_FCOE(bp)) {
|
||||
rtnl_lock();
|
||||
|
@ -14177,3 +14437,332 @@ int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
|
|||
REG_RD(bp, pretend_reg);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void bnx2x_ptp_task(struct work_struct *work)
|
||||
{
|
||||
struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
|
||||
int port = BP_PORT(bp);
|
||||
u32 val_seq;
|
||||
u64 timestamp, ns;
|
||||
struct skb_shared_hwtstamps shhwtstamps;
|
||||
|
||||
/* Read Tx timestamp registers */
|
||||
val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
|
||||
NIG_REG_P0_TLLH_PTP_BUF_SEQID);
|
||||
if (val_seq & 0x10000) {
|
||||
/* There is a valid timestamp value */
|
||||
timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
|
||||
NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
|
||||
timestamp <<= 32;
|
||||
timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
|
||||
NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
|
||||
/* Reset timestamp register to allow new timestamp */
|
||||
REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
|
||||
NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
|
||||
ns = timecounter_cyc2time(&bp->timecounter, timestamp);
|
||||
|
||||
memset(&shhwtstamps, 0, sizeof(shhwtstamps));
|
||||
shhwtstamps.hwtstamp = ns_to_ktime(ns);
|
||||
skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
|
||||
dev_kfree_skb_any(bp->ptp_tx_skb);
|
||||
bp->ptp_tx_skb = NULL;
|
||||
|
||||
DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
|
||||
timestamp, ns);
|
||||
} else {
|
||||
DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
|
||||
/* Reschedule to keep checking for a valid timestamp value */
|
||||
schedule_work(&bp->ptp_task);
|
||||
}
|
||||
}
|
||||
|
||||
void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
|
||||
{
|
||||
int port = BP_PORT(bp);
|
||||
u64 timestamp, ns;
|
||||
|
||||
timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
|
||||
NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
|
||||
timestamp <<= 32;
|
||||
timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
|
||||
NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
|
||||
|
||||
/* Reset timestamp register to allow new timestamp */
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
|
||||
NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
|
||||
|
||||
ns = timecounter_cyc2time(&bp->timecounter, timestamp);
|
||||
|
||||
skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
|
||||
|
||||
DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
|
||||
timestamp, ns);
|
||||
}
|
||||
|
||||
/* Read the PHC */
|
||||
static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
|
||||
{
|
||||
struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
|
||||
int port = BP_PORT(bp);
|
||||
u32 wb_data[2];
|
||||
u64 phc_cycles;
|
||||
|
||||
REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
|
||||
NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
|
||||
phc_cycles = wb_data[1];
|
||||
phc_cycles = (phc_cycles << 32) + wb_data[0];
|
||||
|
||||
DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
|
||||
|
||||
return phc_cycles;
|
||||
}
|
||||
|
||||
static void bnx2x_init_cyclecounter(struct bnx2x *bp)
|
||||
{
|
||||
memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
|
||||
bp->cyclecounter.read = bnx2x_cyclecounter_read;
|
||||
bp->cyclecounter.mask = CLOCKSOURCE_MASK(64);
|
||||
bp->cyclecounter.shift = 1;
|
||||
bp->cyclecounter.mult = 1;
|
||||
}
|
||||
|
||||
static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
|
||||
{
|
||||
struct bnx2x_func_state_params func_params = {NULL};
|
||||
struct bnx2x_func_set_timesync_params *set_timesync_params =
|
||||
&func_params.params.set_timesync;
|
||||
|
||||
/* Prepare parameters for function state transitions */
|
||||
__set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
|
||||
__set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
|
||||
|
||||
func_params.f_obj = &bp->func_obj;
|
||||
func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
|
||||
|
||||
/* Function parameters */
|
||||
set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
|
||||
set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
|
||||
|
||||
return bnx2x_func_state_change(bp, &func_params);
|
||||
}
|
||||
|
||||
int bnx2x_enable_ptp_packets(struct bnx2x *bp)
|
||||
{
|
||||
struct bnx2x_queue_state_params q_params;
|
||||
int rc, i;
|
||||
|
||||
/* send queue update ramrod to enable PTP packets */
|
||||
memset(&q_params, 0, sizeof(q_params));
|
||||
__set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
|
||||
q_params.cmd = BNX2X_Q_CMD_UPDATE;
|
||||
__set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
|
||||
&q_params.params.update.update_flags);
|
||||
__set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
|
||||
&q_params.params.update.update_flags);
|
||||
|
||||
/* send the ramrod on all the queues of the PF */
|
||||
for_each_eth_queue(bp, i) {
|
||||
struct bnx2x_fastpath *fp = &bp->fp[i];
|
||||
|
||||
/* Set the appropriate Queue object */
|
||||
q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
|
||||
|
||||
/* Update the Queue state */
|
||||
rc = bnx2x_queue_state_change(bp, &q_params);
|
||||
if (rc) {
|
||||
BNX2X_ERR("Failed to enable PTP packets\n");
|
||||
return rc;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int bnx2x_configure_ptp_filters(struct bnx2x *bp)
|
||||
{
|
||||
int port = BP_PORT(bp);
|
||||
int rc;
|
||||
|
||||
if (!bp->hwtstamp_ioctl_called)
|
||||
return 0;
|
||||
|
||||
switch (bp->tx_type) {
|
||||
case HWTSTAMP_TX_ON:
|
||||
bp->flags |= TX_TIMESTAMPING_EN;
|
||||
REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
|
||||
NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
|
||||
REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
|
||||
NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
|
||||
break;
|
||||
case HWTSTAMP_TX_ONESTEP_SYNC:
|
||||
BNX2X_ERR("One-step timestamping is not supported\n");
|
||||
return -ERANGE;
|
||||
}
|
||||
|
||||
switch (bp->rx_filter) {
|
||||
case HWTSTAMP_FILTER_NONE:
|
||||
break;
|
||||
case HWTSTAMP_FILTER_ALL:
|
||||
case HWTSTAMP_FILTER_SOME:
|
||||
bp->rx_filter = HWTSTAMP_FILTER_NONE;
|
||||
break;
|
||||
case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
|
||||
case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
|
||||
case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
|
||||
bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
|
||||
/* Initialize PTP detection for UDP/IPv4 events */
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
|
||||
NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
|
||||
NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
|
||||
break;
|
||||
case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
|
||||
case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
|
||||
case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
|
||||
bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
|
||||
/* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
|
||||
NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
|
||||
NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
|
||||
break;
|
||||
case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
|
||||
case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
|
||||
case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
|
||||
bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
|
||||
/* Initialize PTP detection L2 events */
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
|
||||
NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
|
||||
NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
|
||||
|
||||
break;
|
||||
case HWTSTAMP_FILTER_PTP_V2_EVENT:
|
||||
case HWTSTAMP_FILTER_PTP_V2_SYNC:
|
||||
case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
|
||||
bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
|
||||
/* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
|
||||
NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
|
||||
NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Indicate to FW that this PF expects recorded PTP packets */
|
||||
rc = bnx2x_enable_ptp_packets(bp);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
/* Enable sending PTP packets to host */
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
|
||||
NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
|
||||
{
|
||||
struct hwtstamp_config config;
|
||||
int rc;
|
||||
|
||||
DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
|
||||
|
||||
if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
|
||||
return -EFAULT;
|
||||
|
||||
DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
|
||||
config.tx_type, config.rx_filter);
|
||||
|
||||
if (config.flags) {
|
||||
BNX2X_ERR("config.flags is reserved for future use\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
bp->hwtstamp_ioctl_called = 1;
|
||||
bp->tx_type = config.tx_type;
|
||||
bp->rx_filter = config.rx_filter;
|
||||
|
||||
rc = bnx2x_configure_ptp_filters(bp);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
config.rx_filter = bp->rx_filter;
|
||||
|
||||
return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
|
||||
-EFAULT : 0;
|
||||
}
|
||||
|
||||
/* Configrues HW for PTP */
|
||||
static int bnx2x_configure_ptp(struct bnx2x *bp)
|
||||
{
|
||||
int rc, port = BP_PORT(bp);
|
||||
u32 wb_data[2];
|
||||
|
||||
/* Reset PTP event detection rules - will be configured in the IOCTL */
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
|
||||
NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
|
||||
NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
|
||||
REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
|
||||
NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
|
||||
REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
|
||||
NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
|
||||
|
||||
/* Disable PTP packets to host - will be configured in the IOCTL*/
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
|
||||
NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
|
||||
|
||||
/* Enable the PTP feature */
|
||||
REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
|
||||
NIG_REG_P0_PTP_EN, 0x3F);
|
||||
|
||||
/* Enable the free-running counter */
|
||||
wb_data[0] = 0;
|
||||
wb_data[1] = 0;
|
||||
REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
|
||||
|
||||
/* Reset drift register (offset register is not reset) */
|
||||
rc = bnx2x_send_reset_timesync_ramrod(bp);
|
||||
if (rc) {
|
||||
BNX2X_ERR("Failed to reset PHC drift register\n");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
/* Reset possibly old timestamps */
|
||||
REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
|
||||
NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
|
||||
REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
|
||||
NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Called during load, to initialize PTP-related stuff */
|
||||
void bnx2x_init_ptp(struct bnx2x *bp)
|
||||
{
|
||||
int rc;
|
||||
|
||||
/* Configure PTP in HW */
|
||||
rc = bnx2x_configure_ptp(bp);
|
||||
if (rc) {
|
||||
BNX2X_ERR("Stopping PTP initialization\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Init work queue for Tx timestamping */
|
||||
INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
|
||||
|
||||
/* Init cyclecounter and timecounter. This is done only in the first
|
||||
* load. If done in every load, PTP application will fail when doing
|
||||
* unload / load (e.g. MTU change) while it is running.
|
||||
*/
|
||||
if (!bp->timecounter_init_done) {
|
||||
bnx2x_init_cyclecounter(bp);
|
||||
timecounter_init(&bp->timecounter, &bp->cyclecounter,
|
||||
ktime_to_ns(ktime_get_real()));
|
||||
bp->timecounter_init_done = 1;
|
||||
}
|
||||
|
||||
DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
|
||||
}
|
||||
|
|
|
@ -2182,6 +2182,45 @@
|
|||
#define NIG_REG_P0_HWPFC_ENABLE 0x18078
|
||||
#define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
|
||||
#define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440
|
||||
/* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
|
||||
* the host. Bits [15:0] return the sequence ID of the packet. Bit 16
|
||||
* indicates the validity of the data in the buffer. Writing a 1 to bit 16
|
||||
* will clear the buffer.
|
||||
*/
|
||||
#define NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID 0x1875c
|
||||
/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
|
||||
* the host. This location returns the lower 32 bits of timestamp value.
|
||||
*/
|
||||
#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB 0x18754
|
||||
/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
|
||||
* the host. This location returns the upper 32 bits of timestamp value.
|
||||
*/
|
||||
#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB 0x18758
|
||||
/* [RW 11] Mask register for the various parameters used in determining PTP
|
||||
* packet presence. Set each bit to 1 to mask out the particular parameter.
|
||||
* 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
|
||||
* 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
|
||||
* destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
|
||||
* Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
|
||||
* 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
|
||||
* MAC DA 2. The reset default is set to mask out all parameters.
|
||||
*/
|
||||
#define NIG_REG_P0_LLH_PTP_PARAM_MASK 0x187a0
|
||||
/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
|
||||
* each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
|
||||
* 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
|
||||
* 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
|
||||
* UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
|
||||
* DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
|
||||
* 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
|
||||
* default is to mask out all of the rules. Note that rules 0-3 are for IPv4
|
||||
* packets only and require that the packet is IPv4 for the rules to match.
|
||||
* Note that rules 4-7 are for IPv6 packets only and require that the packet
|
||||
* is IPv6 for the rules to match.
|
||||
*/
|
||||
#define NIG_REG_P0_LLH_PTP_RULE_MASK 0x187a4
|
||||
/* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */
|
||||
#define NIG_REG_P0_LLH_PTP_TO_HOST 0x187ac
|
||||
/* [RW 1] Input enable for RX MAC interface. */
|
||||
#define NIG_REG_P0_MAC_IN_EN 0x185ac
|
||||
/* [RW 1] Output enable for TX MAC interface */
|
||||
|
@ -2194,6 +2233,17 @@
|
|||
* priority field is extracted from the outer-most VLAN in receive packet.
|
||||
* Only COS 0 and COS 1 are supported in E2. */
|
||||
#define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054
|
||||
/* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
|
||||
* [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
|
||||
* V1 frame format in timesync event detection on RX side. Bit 2 enables V2
|
||||
* frame format in timesync event detection on RX side. Bit 3 enables
|
||||
* TimeSync on TX side. Bit 4 enables V1 frame format in timesync event
|
||||
* detection on TX side. Bit 5 enables V2 frame format in timesync event
|
||||
* detection on TX side. Note that for HW to detect PTP packet and extract
|
||||
* data from the packet, at least one of the version bits of that traffic
|
||||
* direction has to be enabled.
|
||||
*/
|
||||
#define NIG_REG_P0_PTP_EN 0x18788
|
||||
/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
|
||||
* priority is mapped to COS 0 when the corresponding mask bit is 1. More
|
||||
* than one bit may be set; allowing multiple priorities to be mapped to one
|
||||
|
@ -2300,7 +2350,46 @@
|
|||
* Ethernet header. */
|
||||
#define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c
|
||||
#define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
|
||||
#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460
|
||||
#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460a
|
||||
/* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
|
||||
* the host. Bits [15:0] return the sequence ID of the packet. Bit 16
|
||||
* indicates the validity of the data in the buffer. Writing a 1 to bit 16
|
||||
* will clear the buffer.
|
||||
*/
|
||||
#define NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID 0x18774
|
||||
/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
|
||||
* the host. This location returns the lower 32 bits of timestamp value.
|
||||
*/
|
||||
#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB 0x1876c
|
||||
/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
|
||||
* the host. This location returns the upper 32 bits of timestamp value.
|
||||
*/
|
||||
#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB 0x18770
|
||||
/* [RW 11] Mask register for the various parameters used in determining PTP
|
||||
* packet presence. Set each bit to 1 to mask out the particular parameter.
|
||||
* 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
|
||||
* 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
|
||||
* destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
|
||||
* Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
|
||||
* 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
|
||||
* MAC DA 2. The reset default is set to mask out all parameters.
|
||||
*/
|
||||
#define NIG_REG_P1_LLH_PTP_PARAM_MASK 0x187c8
|
||||
/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
|
||||
* each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
|
||||
* 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
|
||||
* 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
|
||||
* UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
|
||||
* DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
|
||||
* 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
|
||||
* default is to mask out all of the rules. Note that rules 0-3 are for IPv4
|
||||
* packets only and require that the packet is IPv4 for the rules to match.
|
||||
* Note that rules 4-7 are for IPv6 packets only and require that the packet
|
||||
* is IPv6 for the rules to match.
|
||||
*/
|
||||
#define NIG_REG_P1_LLH_PTP_RULE_MASK 0x187cc
|
||||
/* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */
|
||||
#define NIG_REG_P1_LLH_PTP_TO_HOST 0x187d4
|
||||
/* [RW 32] Specify the client number to be assigned to each priority of the
|
||||
* strict priority arbiter. This register specifies bits 31:0 of the 36-bit
|
||||
* value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
|
||||
|
@ -2342,6 +2431,17 @@
|
|||
* priority field is extracted from the outer-most VLAN in receive packet.
|
||||
* Only COS 0 and COS 1 are supported in E2. */
|
||||
#define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8
|
||||
/* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
|
||||
* [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
|
||||
* V1 frame format in timesync event detection on RX side. Bit 2 enables V2
|
||||
* frame format in timesync event detection on RX side. Bit 3 enables
|
||||
* TimeSync on TX side. Bit 4 enables V1 frame format in timesync event
|
||||
* detection on TX side. Bit 5 enables V2 frame format in timesync event
|
||||
* detection on TX side. Note that for HW to detect PTP packet and extract
|
||||
* data from the packet, at least one of the version bits of that traffic
|
||||
* direction has to be enabled.
|
||||
*/
|
||||
#define NIG_REG_P1_PTP_EN 0x187b0
|
||||
/* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
|
||||
* priority is mapped to COS 0 when the corresponding mask bit is 1. More
|
||||
* than one bit may be set; allowing multiple priorities to be mapped to one
|
||||
|
@ -2361,6 +2461,78 @@
|
|||
#define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c
|
||||
/* [R 1] TLLH FIFO is empty. */
|
||||
#define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338
|
||||
/* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
|
||||
* TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16
|
||||
* indicates the validity of the data in the buffer. Bit 17 indicates that
|
||||
* the sequence ID is valid and it is waiting for the TX timestamp value.
|
||||
* Bit 18 indicates whether the timestamp is from a SW request (value of 1)
|
||||
* or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.
|
||||
*/
|
||||
#define NIG_REG_P0_TLLH_PTP_BUF_SEQID 0x187e0
|
||||
/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
|
||||
* MCP. This location returns the lower 32 bits of timestamp value.
|
||||
*/
|
||||
#define NIG_REG_P0_TLLH_PTP_BUF_TS_LSB 0x187d8
|
||||
/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
|
||||
* MCP. This location returns the upper 32 bits of timestamp value.
|
||||
*/
|
||||
#define NIG_REG_P0_TLLH_PTP_BUF_TS_MSB 0x187dc
|
||||
/* [RW 11] Mask register for the various parameters used in determining PTP
|
||||
* packet presence. Set each bit to 1 to mask out the particular parameter.
|
||||
* 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
|
||||
* 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
|
||||
* destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
|
||||
* Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
|
||||
* 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
|
||||
* MAC DA 2. The reset default is set to mask out all parameters.
|
||||
*/
|
||||
#define NIG_REG_P0_TLLH_PTP_PARAM_MASK 0x187f0
|
||||
/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
|
||||
* each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
|
||||
* 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
|
||||
* 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
|
||||
* UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
|
||||
* DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
|
||||
* 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
|
||||
* default is to mask out all of the rules.
|
||||
*/
|
||||
#define NIG_REG_P0_TLLH_PTP_RULE_MASK 0x187f4
|
||||
/* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
|
||||
* TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16
|
||||
* indicates the validity of the data in the buffer. Bit 17 indicates that
|
||||
* the sequence ID is valid and it is waiting for the TX timestamp value.
|
||||
* Bit 18 indicates whether the timestamp is from a SW request (value of 1)
|
||||
* or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.
|
||||
*/
|
||||
#define NIG_REG_P1_TLLH_PTP_BUF_SEQID 0x187ec
|
||||
/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
|
||||
* MCP. This location returns the lower 32 bits of timestamp value.
|
||||
*/
|
||||
#define NIG_REG_P1_TLLH_PTP_BUF_TS_LSB 0x187e4
|
||||
/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
|
||||
* MCP. This location returns the upper 32 bits of timestamp value.
|
||||
*/
|
||||
#define NIG_REG_P1_TLLH_PTP_BUF_TS_MSB 0x187e8
|
||||
/* [RW 11] Mask register for the various parameters used in determining PTP
|
||||
* packet presence. Set each bit to 1 to mask out the particular parameter.
|
||||
* 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
|
||||
* 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
|
||||
* destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
|
||||
* Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
|
||||
* 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
|
||||
* MAC DA 2. The reset default is set to mask out all parameters.
|
||||
*/
|
||||
#define NIG_REG_P1_TLLH_PTP_PARAM_MASK 0x187f8
|
||||
/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
|
||||
* each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
|
||||
* 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
|
||||
* 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
|
||||
* UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
|
||||
* DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
|
||||
* 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
|
||||
* default is to mask out all of the rules.
|
||||
*/
|
||||
#define NIG_REG_P1_TLLH_PTP_RULE_MASK 0x187fc
|
||||
/* [RW 32] Specify which of the credit registers the client is to be mapped
|
||||
* to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
|
||||
* for client 0; bits [35:32] are for client 8. For clients that are not
|
||||
|
@ -2513,6 +2685,10 @@
|
|||
swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
|
||||
ort swap is equal to ~nig_registers_port_swap.port_swap */
|
||||
#define NIG_REG_STRAP_OVERRIDE 0x10398
|
||||
/* [WB 64] Addresses for TimeSync related registers in the timesync
|
||||
* generator sub-module.
|
||||
*/
|
||||
#define NIG_REG_TIMESYNC_GEN_REG 0x18800
|
||||
/* [RW 1] output enable for RX_XCM0 IF */
|
||||
#define NIG_REG_XCM0_OUT_EN 0x100f0
|
||||
/* [RW 1] output enable for RX_XCM1 IF */
|
||||
|
|
|
@ -4725,6 +4725,12 @@ static void bnx2x_q_fill_update_data(struct bnx2x *bp,
|
|||
data->tx_switching_change_flg =
|
||||
test_bit(BNX2X_Q_UPDATE_TX_SWITCHING_CHNG,
|
||||
¶ms->update_flags);
|
||||
|
||||
/* PTP */
|
||||
data->handle_ptp_pkts_flg =
|
||||
test_bit(BNX2X_Q_UPDATE_PTP_PKTS, ¶ms->update_flags);
|
||||
data->handle_ptp_pkts_change_flg =
|
||||
test_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG, ¶ms->update_flags);
|
||||
}
|
||||
|
||||
static inline int bnx2x_q_send_update(struct bnx2x *bp,
|
||||
|
@ -5379,6 +5385,10 @@ static int bnx2x_func_chk_transition(struct bnx2x *bp,
|
|||
(!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
|
||||
next_state = BNX2X_F_STATE_STARTED;
|
||||
|
||||
else if ((cmd == BNX2X_F_CMD_SET_TIMESYNC) &&
|
||||
(!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
|
||||
next_state = BNX2X_F_STATE_STARTED;
|
||||
|
||||
else if (cmd == BNX2X_F_CMD_TX_STOP)
|
||||
next_state = BNX2X_F_STATE_TX_STOPPED;
|
||||
|
||||
|
@ -5388,6 +5398,10 @@ static int bnx2x_func_chk_transition(struct bnx2x *bp,
|
|||
(!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
|
||||
next_state = BNX2X_F_STATE_TX_STOPPED;
|
||||
|
||||
else if ((cmd == BNX2X_F_CMD_SET_TIMESYNC) &&
|
||||
(!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
|
||||
next_state = BNX2X_F_STATE_TX_STOPPED;
|
||||
|
||||
else if (cmd == BNX2X_F_CMD_TX_START)
|
||||
next_state = BNX2X_F_STATE_STARTED;
|
||||
|
||||
|
@ -5843,6 +5857,40 @@ static inline int bnx2x_func_send_tx_start(struct bnx2x *bp,
|
|||
U64_LO(data_mapping), NONE_CONNECTION_TYPE);
|
||||
}
|
||||
|
||||
static inline
|
||||
int bnx2x_func_send_set_timesync(struct bnx2x *bp,
|
||||
struct bnx2x_func_state_params *params)
|
||||
{
|
||||
struct bnx2x_func_sp_obj *o = params->f_obj;
|
||||
struct set_timesync_ramrod_data *rdata =
|
||||
(struct set_timesync_ramrod_data *)o->rdata;
|
||||
dma_addr_t data_mapping = o->rdata_mapping;
|
||||
struct bnx2x_func_set_timesync_params *set_timesync_params =
|
||||
¶ms->params.set_timesync;
|
||||
|
||||
memset(rdata, 0, sizeof(*rdata));
|
||||
|
||||
/* Fill the ramrod data with provided parameters */
|
||||
rdata->drift_adjust_cmd = set_timesync_params->drift_adjust_cmd;
|
||||
rdata->offset_cmd = set_timesync_params->offset_cmd;
|
||||
rdata->add_sub_drift_adjust_value =
|
||||
set_timesync_params->add_sub_drift_adjust_value;
|
||||
rdata->drift_adjust_value = set_timesync_params->drift_adjust_value;
|
||||
rdata->drift_adjust_period = set_timesync_params->drift_adjust_period;
|
||||
rdata->offset_delta.lo = U64_LO(set_timesync_params->offset_delta);
|
||||
rdata->offset_delta.hi = U64_HI(set_timesync_params->offset_delta);
|
||||
|
||||
DP(BNX2X_MSG_SP, "Set timesync command params: drift_cmd = %d, offset_cmd = %d, add_sub_drift = %d, drift_val = %d, drift_period = %d, offset_lo = %d, offset_hi = %d\n",
|
||||
rdata->drift_adjust_cmd, rdata->offset_cmd,
|
||||
rdata->add_sub_drift_adjust_value, rdata->drift_adjust_value,
|
||||
rdata->drift_adjust_period, rdata->offset_delta.lo,
|
||||
rdata->offset_delta.hi);
|
||||
|
||||
return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_TIMESYNC, 0,
|
||||
U64_HI(data_mapping),
|
||||
U64_LO(data_mapping), NONE_CONNECTION_TYPE);
|
||||
}
|
||||
|
||||
static int bnx2x_func_send_cmd(struct bnx2x *bp,
|
||||
struct bnx2x_func_state_params *params)
|
||||
{
|
||||
|
@ -5865,6 +5913,8 @@ static int bnx2x_func_send_cmd(struct bnx2x *bp,
|
|||
return bnx2x_func_send_tx_start(bp, params);
|
||||
case BNX2X_F_CMD_SWITCH_UPDATE:
|
||||
return bnx2x_func_send_switch_update(bp, params);
|
||||
case BNX2X_F_CMD_SET_TIMESYNC:
|
||||
return bnx2x_func_send_set_timesync(bp, params);
|
||||
default:
|
||||
BNX2X_ERR("Unknown command: %d\n", params->cmd);
|
||||
return -EINVAL;
|
||||
|
|
|
@ -770,7 +770,9 @@ enum {
|
|||
BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
|
||||
BNX2X_Q_UPDATE_SILENT_VLAN_REM,
|
||||
BNX2X_Q_UPDATE_TX_SWITCHING_CHNG,
|
||||
BNX2X_Q_UPDATE_TX_SWITCHING
|
||||
BNX2X_Q_UPDATE_TX_SWITCHING,
|
||||
BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
|
||||
BNX2X_Q_UPDATE_PTP_PKTS,
|
||||
};
|
||||
|
||||
/* Allowed Queue states */
|
||||
|
@ -853,6 +855,10 @@ enum bnx2x_q_type {
|
|||
#define BNX2X_MULTI_TX_COS 3 /* Maximum possible */
|
||||
|
||||
#define MAC_PAD (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
|
||||
/* DMAE channel to be used by FW for timesync workaroun. A driver that sends
|
||||
* timesync-related ramrods must not use this DMAE command ID.
|
||||
*/
|
||||
#define FW_DMAE_CMD_ID 6
|
||||
|
||||
struct bnx2x_queue_init_params {
|
||||
struct {
|
||||
|
@ -1117,6 +1123,7 @@ enum bnx2x_func_cmd {
|
|||
BNX2X_F_CMD_TX_STOP,
|
||||
BNX2X_F_CMD_TX_START,
|
||||
BNX2X_F_CMD_SWITCH_UPDATE,
|
||||
BNX2X_F_CMD_SET_TIMESYNC,
|
||||
BNX2X_F_CMD_MAX,
|
||||
};
|
||||
|
||||
|
@ -1191,6 +1198,7 @@ struct bnx2x_func_afex_viflists_params {
|
|||
u8 afex_vif_list_command;
|
||||
u8 func_to_clear;
|
||||
};
|
||||
|
||||
struct bnx2x_func_tx_start_params {
|
||||
struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
|
||||
u8 dcb_enabled;
|
||||
|
@ -1198,6 +1206,24 @@ struct bnx2x_func_tx_start_params {
|
|||
u8 dont_add_pri_0_en;
|
||||
};
|
||||
|
||||
struct bnx2x_func_set_timesync_params {
|
||||
/* Reset, set or keep the current drift value */
|
||||
u8 drift_adjust_cmd;
|
||||
|
||||
/* Dec, inc or keep the current offset */
|
||||
u8 offset_cmd;
|
||||
|
||||
/* Drift value direction */
|
||||
u8 add_sub_drift_adjust_value;
|
||||
|
||||
/* Drift, period and offset values to be used according to the commands
|
||||
* above.
|
||||
*/
|
||||
u8 drift_adjust_value;
|
||||
u32 drift_adjust_period;
|
||||
u64 offset_delta;
|
||||
};
|
||||
|
||||
struct bnx2x_func_state_params {
|
||||
struct bnx2x_func_sp_obj *f_obj;
|
||||
|
||||
|
@ -1216,6 +1242,7 @@ struct bnx2x_func_state_params {
|
|||
struct bnx2x_func_afex_update_params afex_update;
|
||||
struct bnx2x_func_afex_viflists_params afex_viflists;
|
||||
struct bnx2x_func_tx_start_params tx_start;
|
||||
struct bnx2x_func_set_timesync_params set_timesync;
|
||||
} params;
|
||||
};
|
||||
|
||||
|
|
Loading…
Reference in a new issue